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@@ -0,0 +1,109 @@
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+/*
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+ * dts file for Xilinx ZynqMP Mini Configuration
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+ *
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+ * (C) Copyright 2018, Xilinx, Inc.
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+ *
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+ * Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
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+ * Michal Simek <michal.simek@xilinx.com>
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+ *
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+ * SPDX-License-Identifier: GPL-2.0+
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+ */
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+
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+/dts-v1/;
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+
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+/ {
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+ model = "ZynqMP MINI NAND";
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+ compatible = "xlnx,zynqmp";
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+ #address-cells = <2>;
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+ #size-cells = <1>;
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+
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+ aliases {
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+ serial0 = &dcc;
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+ };
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+
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+ chosen {
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+ stdout-path = "serial0:115200n8";
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+ };
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+
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+ memory@0 {
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+ device_type = "memory";
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+ reg = <0x0 0x0 0x40000000>;
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+ };
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+
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+ dcc: dcc {
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+ compatible = "arm,dcc";
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+ status = "disabled";
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+ u-boot,dm-pre-reloc;
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+ };
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+
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+ amba: amba {
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+ compatible = "simple-bus";
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+ #address-cells = <2>;
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+ #size-cells = <1>;
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+ ranges;
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+
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+ nand0: nand@ff100000 {
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+ compatible = "arasan,nfc-v3p10";
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+ status = "okay";
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+ reg = <0x0 0xff100000 0x1000>;
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+ clock-names = "clk_sys", "clk_flash";
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+ #address-cells = <2>;
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+ #size-cells = <1>;
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+ arasan,has-mdma;
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+ num-cs = <2>;
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+
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+ partition@0 { /* for testing purpose */
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+ label = "nand-fsbl-uboot";
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+ reg = <0x0 0x0 0x400000>;
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+ };
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+ partition@1 { /* for testing purpose */
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+ label = "nand-linux";
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+ reg = <0x0 0x400000 0x1400000>;
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+ };
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+ partition@2 { /* for testing purpose */
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+ label = "nand-device-tree";
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+ reg = <0x0 0x1800000 0x400000>;
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+ };
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+ partition@3 { /* for testing purpose */
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+ label = "nand-rootfs";
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+ reg = <0x0 0x1C00000 0x1400000>;
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+ };
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+ partition@4 { /* for testing purpose */
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+ label = "nand-bitstream";
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+ reg = <0x0 0x3000000 0x400000>;
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+ };
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+ partition@5 { /* for testing purpose */
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+ label = "nand-misc";
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+ reg = <0x0 0x3400000 0xFCC00000>;
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+ };
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+ partition@6 { /* for testing purpose */
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+ label = "nand1-fsbl-uboot";
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+ reg = <0x1 0x0 0x400000>;
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+ };
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+ partition@7 { /* for testing purpose */
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+ label = "nand1-linux";
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+ reg = <0x1 0x400000 0x1400000>;
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+ };
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+ partition@8 { /* for testing purpose */
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+ label = "nand1-device-tree";
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+ reg = <0x1 0x1800000 0x400000>;
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+ };
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+ partition@9 { /* for testing purpose */
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+ label = "nand1-rootfs";
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+ reg = <0x1 0x1C00000 0x1400000>;
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+ };
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+ partition@10 { /* for testing purpose */
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+ label = "nand1-bitstream";
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+ reg = <0x1 0x3000000 0x400000>;
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+ };
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+ partition@11 { /* for testing purpose */
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+ label = "nand1-misc";
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+ reg = <0x1 0x3400000 0xFCC00000>;
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+ };
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+ };
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+ };
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+};
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+
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+&dcc {
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+ status = "okay";
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+};
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