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+/*
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+ * Copyright (C) 2012 Altera <www.altera.com>
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License as published by
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+ * the Free Software Foundation; either version 2 of the License, or
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+ * (at your option) any later version.
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+ *
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ *
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+ * You should have received a copy of the GNU General Public License
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+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
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+ */
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+
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+#include "skeleton.dtsi"
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+#include <dt-bindings/reset/altr,rst-mgr.h>
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+
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+/ {
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+
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+ aliases {
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+ ethernet0 = &gmac0;
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+ ethernet1 = &gmac1;
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+ serial0 = &uart0;
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+ serial1 = &uart1;
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+ timer0 = &timer0;
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+ timer1 = &timer1;
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+ timer2 = &timer2;
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+ timer3 = &timer3;
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+ };
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+
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+ cpus {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ cpu@0 {
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+ compatible = "arm,cortex-a9";
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+ device_type = "cpu";
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+ reg = <0>;
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+ next-level-cache = <&L2>;
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+ };
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+ cpu@1 {
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+ compatible = "arm,cortex-a9";
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+ device_type = "cpu";
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+ reg = <1>;
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+ next-level-cache = <&L2>;
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+ };
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+ };
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+
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+ intc: intc@fffed000 {
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+ compatible = "arm,cortex-a9-gic";
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+ #interrupt-cells = <3>;
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+ interrupt-controller;
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+ reg = <0xfffed000 0x1000>,
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+ <0xfffec100 0x100>;
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+ };
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+
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+ soc {
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ compatible = "simple-bus";
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+ device_type = "soc";
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+ interrupt-parent = <&intc>;
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+ ranges;
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+
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+ amba {
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+ compatible = "arm,amba-bus";
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ ranges;
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+
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+ pdma: pdma@ffe01000 {
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+ compatible = "arm,pl330", "arm,primecell";
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+ reg = <0xffe01000 0x1000>;
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+ interrupts = <0 104 4>,
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+ <0 105 4>,
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+ <0 106 4>,
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+ <0 107 4>,
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+ <0 108 4>,
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+ <0 109 4>,
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+ <0 110 4>,
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+ <0 111 4>;
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+ #dma-cells = <1>;
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+ #dma-channels = <8>;
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+ #dma-requests = <32>;
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+ clocks = <&l4_main_clk>;
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+ clock-names = "apb_pclk";
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+ };
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+ };
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+
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+ can0: can@ffc00000 {
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+ compatible = "bosch,d_can";
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+ reg = <0xffc00000 0x1000>;
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+ interrupts = <0 131 4>, <0 132 4>, <0 133 4>, <0 134 4>;
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+ clocks = <&can0_clk>;
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+ status = "disabled";
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+ };
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+
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+ can1: can@ffc01000 {
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+ compatible = "bosch,d_can";
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+ reg = <0xffc01000 0x1000>;
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+ interrupts = <0 135 4>, <0 136 4>, <0 137 4>, <0 138 4>;
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+ clocks = <&can1_clk>;
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+ status = "disabled";
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+ };
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+
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+ clkmgr@ffd04000 {
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+ compatible = "altr,clk-mgr";
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+ reg = <0xffd04000 0x1000>;
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+
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+ clocks {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ osc1: osc1 {
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+ #clock-cells = <0>;
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+ compatible = "fixed-clock";
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+ };
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+
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+ osc2: osc2 {
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+ #clock-cells = <0>;
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+ compatible = "fixed-clock";
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+ };
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+
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+ f2s_periph_ref_clk: f2s_periph_ref_clk {
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+ #clock-cells = <0>;
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+ compatible = "fixed-clock";
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+ };
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+
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+ f2s_sdram_ref_clk: f2s_sdram_ref_clk {
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+ #clock-cells = <0>;
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+ compatible = "fixed-clock";
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+ };
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+
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+ main_pll: main_pll {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ #clock-cells = <0>;
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+ compatible = "altr,socfpga-pll-clock";
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+ clocks = <&osc1>;
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+ reg = <0x40>;
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+
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+ mpuclk: mpuclk {
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+ #clock-cells = <0>;
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+ compatible = "altr,socfpga-perip-clk";
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+ clocks = <&main_pll>;
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+ div-reg = <0xe0 0 9>;
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+ reg = <0x48>;
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+ };
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+
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+ mainclk: mainclk {
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+ #clock-cells = <0>;
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+ compatible = "altr,socfpga-perip-clk";
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+ clocks = <&main_pll>;
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+ div-reg = <0xe4 0 9>;
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+ reg = <0x4C>;
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+ };
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+
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+ dbg_base_clk: dbg_base_clk {
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+ #clock-cells = <0>;
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+ compatible = "altr,socfpga-perip-clk";
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+ clocks = <&main_pll>;
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+ div-reg = <0xe8 0 9>;
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+ reg = <0x50>;
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+ };
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+
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+ main_qspi_clk: main_qspi_clk {
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+ #clock-cells = <0>;
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+ compatible = "altr,socfpga-perip-clk";
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+ clocks = <&main_pll>;
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+ reg = <0x54>;
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+ };
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+
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+ main_nand_sdmmc_clk: main_nand_sdmmc_clk {
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+ #clock-cells = <0>;
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+ compatible = "altr,socfpga-perip-clk";
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+ clocks = <&main_pll>;
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+ reg = <0x58>;
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+ };
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+
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+ cfg_h2f_usr0_clk: cfg_h2f_usr0_clk {
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+ #clock-cells = <0>;
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+ compatible = "altr,socfpga-perip-clk";
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+ clocks = <&main_pll>;
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+ reg = <0x5C>;
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+ };
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+ };
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+
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+ periph_pll: periph_pll {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ #clock-cells = <0>;
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+ compatible = "altr,socfpga-pll-clock";
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+ clocks = <&osc1>, <&osc2>, <&f2s_periph_ref_clk>;
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+ reg = <0x80>;
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+
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+ emac0_clk: emac0_clk {
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+ #clock-cells = <0>;
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+ compatible = "altr,socfpga-perip-clk";
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+ clocks = <&periph_pll>;
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+ reg = <0x88>;
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+ };
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+
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+ emac1_clk: emac1_clk {
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+ #clock-cells = <0>;
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+ compatible = "altr,socfpga-perip-clk";
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+ clocks = <&periph_pll>;
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+ reg = <0x8C>;
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+ };
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+
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+ per_qspi_clk: per_qsi_clk {
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+ #clock-cells = <0>;
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+ compatible = "altr,socfpga-perip-clk";
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+ clocks = <&periph_pll>;
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+ reg = <0x90>;
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+ };
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+
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+ per_nand_mmc_clk: per_nand_mmc_clk {
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+ #clock-cells = <0>;
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+ compatible = "altr,socfpga-perip-clk";
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+ clocks = <&periph_pll>;
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+ reg = <0x94>;
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+ };
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+
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+ per_base_clk: per_base_clk {
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+ #clock-cells = <0>;
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+ compatible = "altr,socfpga-perip-clk";
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+ clocks = <&periph_pll>;
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+ reg = <0x98>;
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+ };
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+
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+ h2f_usr1_clk: h2f_usr1_clk {
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+ #clock-cells = <0>;
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+ compatible = "altr,socfpga-perip-clk";
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+ clocks = <&periph_pll>;
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+ reg = <0x9C>;
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+ };
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+ };
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+
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+ sdram_pll: sdram_pll {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ #clock-cells = <0>;
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+ compatible = "altr,socfpga-pll-clock";
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+ clocks = <&osc1>, <&osc2>, <&f2s_sdram_ref_clk>;
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+ reg = <0xC0>;
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+
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+ ddr_dqs_clk: ddr_dqs_clk {
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+ #clock-cells = <0>;
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+ compatible = "altr,socfpga-perip-clk";
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+ clocks = <&sdram_pll>;
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+ reg = <0xC8>;
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+ };
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+
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+ ddr_2x_dqs_clk: ddr_2x_dqs_clk {
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+ #clock-cells = <0>;
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+ compatible = "altr,socfpga-perip-clk";
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+ clocks = <&sdram_pll>;
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+ reg = <0xCC>;
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+ };
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+
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+ ddr_dq_clk: ddr_dq_clk {
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+ #clock-cells = <0>;
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+ compatible = "altr,socfpga-perip-clk";
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+ clocks = <&sdram_pll>;
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+ reg = <0xD0>;
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+ };
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+
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+ h2f_usr2_clk: h2f_usr2_clk {
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+ #clock-cells = <0>;
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+ compatible = "altr,socfpga-perip-clk";
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+ clocks = <&sdram_pll>;
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+ reg = <0xD4>;
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+ };
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+ };
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+
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+ mpu_periph_clk: mpu_periph_clk {
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+ #clock-cells = <0>;
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+ compatible = "altr,socfpga-perip-clk";
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+ clocks = <&mpuclk>;
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+ fixed-divider = <4>;
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+ };
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+
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+ mpu_l2_ram_clk: mpu_l2_ram_clk {
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+ #clock-cells = <0>;
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+ compatible = "altr,socfpga-perip-clk";
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+ clocks = <&mpuclk>;
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+ fixed-divider = <2>;
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+ };
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+
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+ l4_main_clk: l4_main_clk {
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+ #clock-cells = <0>;
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+ compatible = "altr,socfpga-gate-clk";
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+ clocks = <&mainclk>;
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+ clk-gate = <0x60 0>;
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+ };
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+
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+ l3_main_clk: l3_main_clk {
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+ #clock-cells = <0>;
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+ compatible = "altr,socfpga-perip-clk";
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+ clocks = <&mainclk>;
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+ fixed-divider = <1>;
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+ };
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+
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+ l3_mp_clk: l3_mp_clk {
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+ #clock-cells = <0>;
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+ compatible = "altr,socfpga-gate-clk";
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+ clocks = <&mainclk>;
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+ div-reg = <0x64 0 2>;
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+ clk-gate = <0x60 1>;
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+ };
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+
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+ l3_sp_clk: l3_sp_clk {
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+ #clock-cells = <0>;
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+ compatible = "altr,socfpga-gate-clk";
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+ clocks = <&mainclk>;
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+ div-reg = <0x64 2 2>;
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+ };
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+
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+ l4_mp_clk: l4_mp_clk {
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+ #clock-cells = <0>;
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+ compatible = "altr,socfpga-gate-clk";
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+ clocks = <&mainclk>, <&per_base_clk>;
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+ div-reg = <0x64 4 3>;
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+ clk-gate = <0x60 2>;
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+ };
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+
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+ l4_sp_clk: l4_sp_clk {
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+ #clock-cells = <0>;
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+ compatible = "altr,socfpga-gate-clk";
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+ clocks = <&mainclk>, <&per_base_clk>;
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+ div-reg = <0x64 7 3>;
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+ clk-gate = <0x60 3>;
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+ };
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+
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+ dbg_at_clk: dbg_at_clk {
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+ #clock-cells = <0>;
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+ compatible = "altr,socfpga-gate-clk";
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+ clocks = <&dbg_base_clk>;
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+ div-reg = <0x68 0 2>;
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+ clk-gate = <0x60 4>;
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+ };
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+
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+ dbg_clk: dbg_clk {
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+ #clock-cells = <0>;
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+ compatible = "altr,socfpga-gate-clk";
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+ clocks = <&dbg_base_clk>;
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+ div-reg = <0x68 2 2>;
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+ clk-gate = <0x60 5>;
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+ };
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+
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+ dbg_trace_clk: dbg_trace_clk {
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+ #clock-cells = <0>;
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+ compatible = "altr,socfpga-gate-clk";
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+ clocks = <&dbg_base_clk>;
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+ div-reg = <0x6C 0 3>;
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+ clk-gate = <0x60 6>;
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+ };
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+
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+ dbg_timer_clk: dbg_timer_clk {
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+ #clock-cells = <0>;
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+ compatible = "altr,socfpga-gate-clk";
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+ clocks = <&dbg_base_clk>;
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+ clk-gate = <0x60 7>;
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+ };
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+
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+ cfg_clk: cfg_clk {
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+ #clock-cells = <0>;
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+ compatible = "altr,socfpga-gate-clk";
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+ clocks = <&cfg_h2f_usr0_clk>;
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+ clk-gate = <0x60 8>;
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+ };
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+
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+ h2f_user0_clk: h2f_user0_clk {
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+ #clock-cells = <0>;
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+ compatible = "altr,socfpga-gate-clk";
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+ clocks = <&cfg_h2f_usr0_clk>;
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+ clk-gate = <0x60 9>;
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+ };
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+
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+ emac_0_clk: emac_0_clk {
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+ #clock-cells = <0>;
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+ compatible = "altr,socfpga-gate-clk";
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+ clocks = <&emac0_clk>;
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+ clk-gate = <0xa0 0>;
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+ };
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+
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+ emac_1_clk: emac_1_clk {
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+ #clock-cells = <0>;
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+ compatible = "altr,socfpga-gate-clk";
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+ clocks = <&emac1_clk>;
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+ clk-gate = <0xa0 1>;
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+ };
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+
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+ usb_mp_clk: usb_mp_clk {
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+ #clock-cells = <0>;
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+ compatible = "altr,socfpga-gate-clk";
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+ clocks = <&per_base_clk>;
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+ clk-gate = <0xa0 2>;
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+ div-reg = <0xa4 0 3>;
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+ };
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+
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+ spi_m_clk: spi_m_clk {
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+ #clock-cells = <0>;
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+ compatible = "altr,socfpga-gate-clk";
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+ clocks = <&per_base_clk>;
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+ clk-gate = <0xa0 3>;
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+ div-reg = <0xa4 3 3>;
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+ };
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+
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|
+ can0_clk: can0_clk {
|
|
|
+ #clock-cells = <0>;
|
|
|
+ compatible = "altr,socfpga-gate-clk";
|
|
|
+ clocks = <&per_base_clk>;
|
|
|
+ clk-gate = <0xa0 4>;
|
|
|
+ div-reg = <0xa4 6 3>;
|
|
|
+ };
|
|
|
+
|
|
|
+ can1_clk: can1_clk {
|
|
|
+ #clock-cells = <0>;
|
|
|
+ compatible = "altr,socfpga-gate-clk";
|
|
|
+ clocks = <&per_base_clk>;
|
|
|
+ clk-gate = <0xa0 5>;
|
|
|
+ div-reg = <0xa4 9 3>;
|
|
|
+ };
|
|
|
+
|
|
|
+ gpio_db_clk: gpio_db_clk {
|
|
|
+ #clock-cells = <0>;
|
|
|
+ compatible = "altr,socfpga-gate-clk";
|
|
|
+ clocks = <&per_base_clk>;
|
|
|
+ clk-gate = <0xa0 6>;
|
|
|
+ div-reg = <0xa8 0 24>;
|
|
|
+ };
|
|
|
+
|
|
|
+ h2f_user1_clk: h2f_user1_clk {
|
|
|
+ #clock-cells = <0>;
|
|
|
+ compatible = "altr,socfpga-gate-clk";
|
|
|
+ clocks = <&h2f_usr1_clk>;
|
|
|
+ clk-gate = <0xa0 7>;
|
|
|
+ };
|
|
|
+
|
|
|
+ sdmmc_clk: sdmmc_clk {
|
|
|
+ #clock-cells = <0>;
|
|
|
+ compatible = "altr,socfpga-gate-clk";
|
|
|
+ clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
|
|
|
+ clk-gate = <0xa0 8>;
|
|
|
+ clk-phase = <0 135>;
|
|
|
+ };
|
|
|
+
|
|
|
+ nand_x_clk: nand_x_clk {
|
|
|
+ #clock-cells = <0>;
|
|
|
+ compatible = "altr,socfpga-gate-clk";
|
|
|
+ clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
|
|
|
+ clk-gate = <0xa0 9>;
|
|
|
+ };
|
|
|
+
|
|
|
+ nand_clk: nand_clk {
|
|
|
+ #clock-cells = <0>;
|
|
|
+ compatible = "altr,socfpga-gate-clk";
|
|
|
+ clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
|
|
|
+ clk-gate = <0xa0 10>;
|
|
|
+ fixed-divider = <4>;
|
|
|
+ };
|
|
|
+
|
|
|
+ qspi_clk: qspi_clk {
|
|
|
+ #clock-cells = <0>;
|
|
|
+ compatible = "altr,socfpga-gate-clk";
|
|
|
+ clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>;
|
|
|
+ clk-gate = <0xa0 11>;
|
|
|
+ };
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ gmac0: ethernet@ff700000 {
|
|
|
+ compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
|
|
|
+ altr,sysmgr-syscon = <&sysmgr 0x60 0>;
|
|
|
+ reg = <0xff700000 0x2000>;
|
|
|
+ interrupts = <0 115 4>;
|
|
|
+ interrupt-names = "macirq";
|
|
|
+ mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
|
|
|
+ clocks = <&emac0_clk>;
|
|
|
+ clock-names = "stmmaceth";
|
|
|
+ resets = <&rst EMAC0_RESET>;
|
|
|
+ reset-names = "stmmaceth";
|
|
|
+ snps,multicast-filter-bins = <256>;
|
|
|
+ snps,perfect-filter-entries = <128>;
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ gmac1: ethernet@ff702000 {
|
|
|
+ compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
|
|
|
+ altr,sysmgr-syscon = <&sysmgr 0x60 2>;
|
|
|
+ reg = <0xff702000 0x2000>;
|
|
|
+ interrupts = <0 120 4>;
|
|
|
+ interrupt-names = "macirq";
|
|
|
+ mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
|
|
|
+ clocks = <&emac1_clk>;
|
|
|
+ clock-names = "stmmaceth";
|
|
|
+ resets = <&rst EMAC1_RESET>;
|
|
|
+ reset-names = "stmmaceth";
|
|
|
+ snps,multicast-filter-bins = <256>;
|
|
|
+ snps,perfect-filter-entries = <128>;
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ i2c0: i2c@ffc04000 {
|
|
|
+ #address-cells = <1>;
|
|
|
+ #size-cells = <0>;
|
|
|
+ compatible = "snps,designware-i2c";
|
|
|
+ reg = <0xffc04000 0x1000>;
|
|
|
+ clocks = <&l4_sp_clk>;
|
|
|
+ interrupts = <0 158 0x4>;
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ i2c1: i2c@ffc05000 {
|
|
|
+ #address-cells = <1>;
|
|
|
+ #size-cells = <0>;
|
|
|
+ compatible = "snps,designware-i2c";
|
|
|
+ reg = <0xffc05000 0x1000>;
|
|
|
+ clocks = <&l4_sp_clk>;
|
|
|
+ interrupts = <0 159 0x4>;
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ i2c2: i2c@ffc06000 {
|
|
|
+ #address-cells = <1>;
|
|
|
+ #size-cells = <0>;
|
|
|
+ compatible = "snps,designware-i2c";
|
|
|
+ reg = <0xffc06000 0x1000>;
|
|
|
+ clocks = <&l4_sp_clk>;
|
|
|
+ interrupts = <0 160 0x4>;
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ i2c3: i2c@ffc07000 {
|
|
|
+ #address-cells = <1>;
|
|
|
+ #size-cells = <0>;
|
|
|
+ compatible = "snps,designware-i2c";
|
|
|
+ reg = <0xffc07000 0x1000>;
|
|
|
+ clocks = <&l4_sp_clk>;
|
|
|
+ interrupts = <0 161 0x4>;
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ gpio0: gpio@ff708000 {
|
|
|
+ #address-cells = <1>;
|
|
|
+ #size-cells = <0>;
|
|
|
+ compatible = "snps,dw-apb-gpio";
|
|
|
+ reg = <0xff708000 0x1000>;
|
|
|
+ clocks = <&per_base_clk>;
|
|
|
+ status = "disabled";
|
|
|
+
|
|
|
+ porta: gpio-controller@0 {
|
|
|
+ compatible = "snps,dw-apb-gpio-port";
|
|
|
+ gpio-controller;
|
|
|
+ #gpio-cells = <2>;
|
|
|
+ snps,nr-gpios = <29>;
|
|
|
+ reg = <0>;
|
|
|
+ interrupt-controller;
|
|
|
+ #interrupt-cells = <2>;
|
|
|
+ interrupts = <0 164 4>;
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ gpio1: gpio@ff709000 {
|
|
|
+ #address-cells = <1>;
|
|
|
+ #size-cells = <0>;
|
|
|
+ compatible = "snps,dw-apb-gpio";
|
|
|
+ reg = <0xff709000 0x1000>;
|
|
|
+ clocks = <&per_base_clk>;
|
|
|
+ status = "disabled";
|
|
|
+
|
|
|
+ portb: gpio-controller@0 {
|
|
|
+ compatible = "snps,dw-apb-gpio-port";
|
|
|
+ gpio-controller;
|
|
|
+ #gpio-cells = <2>;
|
|
|
+ snps,nr-gpios = <29>;
|
|
|
+ reg = <0>;
|
|
|
+ interrupt-controller;
|
|
|
+ #interrupt-cells = <2>;
|
|
|
+ interrupts = <0 165 4>;
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ gpio2: gpio@ff70a000 {
|
|
|
+ #address-cells = <1>;
|
|
|
+ #size-cells = <0>;
|
|
|
+ compatible = "snps,dw-apb-gpio";
|
|
|
+ reg = <0xff70a000 0x1000>;
|
|
|
+ clocks = <&per_base_clk>;
|
|
|
+ status = "disabled";
|
|
|
+
|
|
|
+ portc: gpio-controller@0 {
|
|
|
+ compatible = "snps,dw-apb-gpio-port";
|
|
|
+ gpio-controller;
|
|
|
+ #gpio-cells = <2>;
|
|
|
+ snps,nr-gpios = <27>;
|
|
|
+ reg = <0>;
|
|
|
+ interrupt-controller;
|
|
|
+ #interrupt-cells = <2>;
|
|
|
+ interrupts = <0 166 4>;
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ sdr: sdr@ffc25000 {
|
|
|
+ compatible = "syscon";
|
|
|
+ reg = <0xffc25000 0x1000>;
|
|
|
+ };
|
|
|
+
|
|
|
+ sdramedac {
|
|
|
+ compatible = "altr,sdram-edac";
|
|
|
+ altr,sdr-syscon = <&sdr>;
|
|
|
+ interrupts = <0 39 4>;
|
|
|
+ };
|
|
|
+
|
|
|
+ L2: l2-cache@fffef000 {
|
|
|
+ compatible = "arm,pl310-cache";
|
|
|
+ reg = <0xfffef000 0x1000>;
|
|
|
+ interrupts = <0 38 0x04>;
|
|
|
+ cache-unified;
|
|
|
+ cache-level = <2>;
|
|
|
+ arm,tag-latency = <1 1 1>;
|
|
|
+ arm,data-latency = <2 1 1>;
|
|
|
+ };
|
|
|
+
|
|
|
+ mmc: dwmmc0@ff704000 {
|
|
|
+ compatible = "altr,socfpga-dw-mshc";
|
|
|
+ reg = <0xff704000 0x1000>;
|
|
|
+ interrupts = <0 139 4>;
|
|
|
+ fifo-depth = <0x400>;
|
|
|
+ #address-cells = <1>;
|
|
|
+ #size-cells = <0>;
|
|
|
+ clocks = <&l4_mp_clk>, <&sdmmc_clk>;
|
|
|
+ clock-names = "biu", "ciu";
|
|
|
+ };
|
|
|
+
|
|
|
+ /* Local timer */
|
|
|
+ timer@fffec600 {
|
|
|
+ compatible = "arm,cortex-a9-twd-timer";
|
|
|
+ reg = <0xfffec600 0x100>;
|
|
|
+ interrupts = <1 13 0xf04>;
|
|
|
+ clocks = <&mpu_periph_clk>;
|
|
|
+ };
|
|
|
+
|
|
|
+ timer0: timer0@ffc08000 {
|
|
|
+ compatible = "snps,dw-apb-timer";
|
|
|
+ interrupts = <0 167 4>;
|
|
|
+ reg = <0xffc08000 0x1000>;
|
|
|
+ clocks = <&l4_sp_clk>;
|
|
|
+ clock-names = "timer";
|
|
|
+ };
|
|
|
+
|
|
|
+ timer1: timer1@ffc09000 {
|
|
|
+ compatible = "snps,dw-apb-timer";
|
|
|
+ interrupts = <0 168 4>;
|
|
|
+ reg = <0xffc09000 0x1000>;
|
|
|
+ clocks = <&l4_sp_clk>;
|
|
|
+ clock-names = "timer";
|
|
|
+ };
|
|
|
+
|
|
|
+ timer2: timer2@ffd00000 {
|
|
|
+ compatible = "snps,dw-apb-timer";
|
|
|
+ interrupts = <0 169 4>;
|
|
|
+ reg = <0xffd00000 0x1000>;
|
|
|
+ clocks = <&osc1>;
|
|
|
+ clock-names = "timer";
|
|
|
+ };
|
|
|
+
|
|
|
+ timer3: timer3@ffd01000 {
|
|
|
+ compatible = "snps,dw-apb-timer";
|
|
|
+ interrupts = <0 170 4>;
|
|
|
+ reg = <0xffd01000 0x1000>;
|
|
|
+ clocks = <&osc1>;
|
|
|
+ clock-names = "timer";
|
|
|
+ };
|
|
|
+
|
|
|
+ uart0: serial0@ffc02000 {
|
|
|
+ compatible = "snps,dw-apb-uart";
|
|
|
+ reg = <0xffc02000 0x1000>;
|
|
|
+ interrupts = <0 162 4>;
|
|
|
+ reg-shift = <2>;
|
|
|
+ reg-io-width = <4>;
|
|
|
+ clocks = <&l4_sp_clk>;
|
|
|
+ };
|
|
|
+
|
|
|
+ uart1: serial1@ffc03000 {
|
|
|
+ compatible = "snps,dw-apb-uart";
|
|
|
+ reg = <0xffc03000 0x1000>;
|
|
|
+ interrupts = <0 163 4>;
|
|
|
+ reg-shift = <2>;
|
|
|
+ reg-io-width = <4>;
|
|
|
+ clocks = <&l4_sp_clk>;
|
|
|
+ };
|
|
|
+
|
|
|
+ rst: rstmgr@ffd05000 {
|
|
|
+ #reset-cells = <1>;
|
|
|
+ compatible = "altr,rst-mgr";
|
|
|
+ reg = <0xffd05000 0x1000>;
|
|
|
+ };
|
|
|
+
|
|
|
+ usbphy0: usbphy@0 {
|
|
|
+ #phy-cells = <0>;
|
|
|
+ compatible = "usb-nop-xceiv";
|
|
|
+ status = "okay";
|
|
|
+ };
|
|
|
+
|
|
|
+ usb0: usb@ffb00000 {
|
|
|
+ compatible = "snps,dwc2";
|
|
|
+ reg = <0xffb00000 0xffff>;
|
|
|
+ interrupts = <0 125 4>;
|
|
|
+ clocks = <&usb_mp_clk>;
|
|
|
+ clock-names = "otg";
|
|
|
+ phys = <&usbphy0>;
|
|
|
+ phy-names = "usb2-phy";
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ usb1: usb@ffb40000 {
|
|
|
+ compatible = "snps,dwc2";
|
|
|
+ reg = <0xffb40000 0xffff>;
|
|
|
+ interrupts = <0 128 4>;
|
|
|
+ clocks = <&usb_mp_clk>;
|
|
|
+ clock-names = "otg";
|
|
|
+ phys = <&usbphy0>;
|
|
|
+ phy-names = "usb2-phy";
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ watchdog0: watchdog@ffd02000 {
|
|
|
+ compatible = "snps,dw-wdt";
|
|
|
+ reg = <0xffd02000 0x1000>;
|
|
|
+ interrupts = <0 171 4>;
|
|
|
+ clocks = <&osc1>;
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ watchdog1: watchdog@ffd03000 {
|
|
|
+ compatible = "snps,dw-wdt";
|
|
|
+ reg = <0xffd03000 0x1000>;
|
|
|
+ interrupts = <0 172 4>;
|
|
|
+ clocks = <&osc1>;
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ sysmgr: sysmgr@ffd08000 {
|
|
|
+ compatible = "altr,sys-mgr", "syscon";
|
|
|
+ reg = <0xffd08000 0x4000>;
|
|
|
+ };
|
|
|
+ };
|
|
|
+};
|