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@@ -46,7 +46,7 @@ static int ls_ep_set_bar(struct udevice *dev, uint fn, struct pci_bar *ep_bar)
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else
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type = PCIE_ATU_TYPE_IO;
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- ls_pcie_atu_inbound_set(pcie, idx, bar, bar_phys, type);
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+ ls_pcie_atu_inbound_set(pcie, fn, type, idx, bar, bar_phys);
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dbi_writel(pcie, lower_32_bits(size - 1), reg + PCIE_NO_SRIOV_BAR_BASE);
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dbi_writel(pcie, flags, reg);
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@@ -64,51 +64,61 @@ static struct pci_ep_ops ls_pcie_ep_ops = {
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.set_bar = ls_ep_set_bar,
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};
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-static void ls_pcie_ep_setup_atu(struct ls_pcie_ep *pcie_ep)
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+static void ls_pcie_ep_setup_atu(struct ls_pcie_ep *pcie_ep, u32 pf)
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{
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struct ls_pcie *pcie = pcie_ep->pcie;
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- u64 phys = CONFIG_SYS_PCI_EP_MEMORY_BASE;
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+ u64 phys = 0;
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+ phys = CONFIG_SYS_PCI_EP_MEMORY_BASE + pf * SZ_64M;
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+
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+ phys = ALIGN(phys, PCIE_BAR0_SIZE);
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/* ATU 0 : INBOUND : map BAR0 */
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- ls_pcie_atu_inbound_set(pcie, 0, PCIE_ATU_TYPE_MEM, 0, phys);
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+ ls_pcie_atu_inbound_set(pcie, pf, PCIE_ATU_TYPE_MEM,
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+ 0 + pf * BAR_NUM, 0, phys);
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/* ATU 1 : INBOUND : map BAR1 */
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- phys += PCIE_BAR1_SIZE;
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- ls_pcie_atu_inbound_set(pcie, 1, PCIE_ATU_TYPE_MEM, 1, phys);
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+ phys = ALIGN(phys + PCIE_BAR0_SIZE, PCIE_BAR1_SIZE);
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+ ls_pcie_atu_inbound_set(pcie, pf, PCIE_ATU_TYPE_MEM,
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+ 1 + pf * BAR_NUM, 1, phys);
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/* ATU 2 : INBOUND : map BAR2 */
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- phys += PCIE_BAR2_SIZE;
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- ls_pcie_atu_inbound_set(pcie, 2, PCIE_ATU_TYPE_MEM, 2, phys);
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- /* ATU 3 : INBOUND : map BAR4 */
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- phys = CONFIG_SYS_PCI_EP_MEMORY_BASE + PCIE_BAR4_SIZE;
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- ls_pcie_atu_inbound_set(pcie, 3, PCIE_ATU_TYPE_MEM, 4, phys);
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-
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- /* ATU 0 : OUTBOUND : map MEM */
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- ls_pcie_atu_outbound_set(pcie, 0,
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- PCIE_ATU_TYPE_MEM,
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- pcie_ep->addr_res.start,
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- 0,
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- CONFIG_SYS_PCI_MEMORY_SIZE);
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+ phys = ALIGN(phys + PCIE_BAR1_SIZE, PCIE_BAR2_SIZE);
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+ ls_pcie_atu_inbound_set(pcie, pf, PCIE_ATU_TYPE_MEM,
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+ 2 + pf * BAR_NUM, 2, phys);
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+ /* ATU 3 : INBOUND : map BAR2 */
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+ phys = ALIGN(phys + PCIE_BAR2_SIZE, PCIE_BAR4_SIZE);
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+ ls_pcie_atu_inbound_set(pcie, pf, PCIE_ATU_TYPE_MEM,
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+ 3 + pf * BAR_NUM, 4, phys);
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+
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+ /* ATU: OUTBOUND : map MEM */
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+ ls_pcie_atu_outbound_set(pcie, pf, PCIE_ATU_TYPE_MEM,
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+ (u64)pcie_ep->addr_res.start +
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+ pf * CONFIG_SYS_PCI_MEMORY_SIZE,
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+ 0, CONFIG_SYS_PCI_MEMORY_SIZE);
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}
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/* BAR0 and BAR1 are 32bit BAR2 and BAR4 are 64bit */
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static void ls_pcie_ep_setup_bar(void *bar_base, int bar, u32 size)
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{
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+ u32 mask;
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+
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/* The least inbound window is 4KiB */
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- if (size < 4 * 1024)
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- return;
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+ if (size < SZ_4K)
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+ mask = 0;
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+ else
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+ mask = size - 1;
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switch (bar) {
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case 0:
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- writel(size - 1, bar_base + PCI_BASE_ADDRESS_0);
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+ writel(mask, bar_base + PCI_BASE_ADDRESS_0);
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break;
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case 1:
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- writel(size - 1, bar_base + PCI_BASE_ADDRESS_1);
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+ writel(mask, bar_base + PCI_BASE_ADDRESS_1);
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break;
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case 2:
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- writel(size - 1, bar_base + PCI_BASE_ADDRESS_2);
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+ writel(mask, bar_base + PCI_BASE_ADDRESS_2);
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writel(0, bar_base + PCI_BASE_ADDRESS_3);
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break;
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case 4:
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- writel(size - 1, bar_base + PCI_BASE_ADDRESS_4);
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+ writel(mask, bar_base + PCI_BASE_ADDRESS_4);
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writel(0, bar_base + PCI_BASE_ADDRESS_5);
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break;
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default:
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@@ -118,39 +128,62 @@ static void ls_pcie_ep_setup_bar(void *bar_base, int bar, u32 size)
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static void ls_pcie_ep_setup_bars(void *bar_base)
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{
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- /* BAR0 - 32bit - 4K configuration */
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+ /* BAR0 - 32bit - MEM */
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+ ls_pcie_ep_setup_bar(bar_base, 0, PCIE_BAR0_SIZE);
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+ /* BAR1 - 32bit - MEM*/
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+ ls_pcie_ep_setup_bar(bar_base, 1, PCIE_BAR1_SIZE);
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+ /* BAR2 - 64bit - MEM */
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+ ls_pcie_ep_setup_bar(bar_base, 2, PCIE_BAR2_SIZE);
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+ /* BAR4 - 64bit - MEM */
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+ ls_pcie_ep_setup_bar(bar_base, 4, PCIE_BAR4_SIZE);
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+}
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+
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+static void ls_pcie_ep_setup_vf_bars(void *bar_base)
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+{
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+ /* VF BAR0 MASK register at offset 0x19c*/
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+ bar_base += PCIE_SRIOV_VFBAR0 - PCI_BASE_ADDRESS_0;
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+
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+ /* VF-BAR0 - 32bit - MEM */
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ls_pcie_ep_setup_bar(bar_base, 0, PCIE_BAR0_SIZE);
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- /* BAR1 - 32bit - 8K MSIX */
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+ /* VF-BAR1 - 32bit - MEM*/
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ls_pcie_ep_setup_bar(bar_base, 1, PCIE_BAR1_SIZE);
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- /* BAR2 - 64bit - 4K MEM descriptor */
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+ /* VF-BAR2 - 64bit - MEM */
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ls_pcie_ep_setup_bar(bar_base, 2, PCIE_BAR2_SIZE);
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- /* BAR4 - 64bit - 1M MEM */
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+ /* VF-BAR4 - 64bit - MEM */
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ls_pcie_ep_setup_bar(bar_base, 4, PCIE_BAR4_SIZE);
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}
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static void ls_pcie_setup_ep(struct ls_pcie_ep *pcie_ep)
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{
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u32 sriov;
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+ u32 pf, vf;
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+ void *bar_base = NULL;
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struct ls_pcie *pcie = pcie_ep->pcie;
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sriov = readl(pcie->dbi + PCIE_SRIOV);
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if (PCI_EXT_CAP_ID(sriov) == PCI_EXT_CAP_ID_SRIOV) {
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- int pf, vf;
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-
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+ pcie_ep->sriov_flag = 1;
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for (pf = 0; pf < PCIE_PF_NUM; pf++) {
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- for (vf = 0; vf <= PCIE_VF_NUM; vf++) {
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- ctrl_writel(pcie, PCIE_LCTRL0_VAL(pf, vf),
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- PCIE_PF_VF_CTRL);
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-
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- ls_pcie_ep_setup_bars(pcie->dbi);
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- ls_pcie_ep_setup_atu(pcie_ep);
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+ if (pcie_ep->cfg2_flag) {
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+ for (vf = 0; vf <= PCIE_VF_NUM; vf++) {
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+ ctrl_writel(pcie,
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+ PCIE_LCTRL0_VAL(pf, vf),
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+ PCIE_PF_VF_CTRL);
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+ }
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}
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+ bar_base = pcie->dbi +
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+ PCIE_MASK_OFFSET(pcie_ep->cfg2_flag, pf);
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+ ls_pcie_ep_setup_bars(bar_base);
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+ ls_pcie_ep_setup_vf_bars(bar_base);
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+
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+ ls_pcie_ep_setup_atu(pcie_ep, pf);
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}
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- /* Disable CFG2 */
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- ctrl_writel(pcie, 0, PCIE_PF_VF_CTRL);
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+
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+ if (pcie_ep->cfg2_flag) /* Disable CFG2 */
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+ ctrl_writel(pcie, 0, PCIE_PF_VF_CTRL);
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} else {
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ls_pcie_ep_setup_bars(pcie->dbi + PCIE_NO_SRIOV_BAR_BASE);
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- ls_pcie_ep_setup_atu(pcie_ep);
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+ ls_pcie_ep_setup_atu(pcie_ep, 0);
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}
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ls_pcie_ep_enable_cfg(pcie_ep);
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@@ -162,6 +195,7 @@ static int ls_pcie_ep_probe(struct udevice *dev)
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struct ls_pcie *pcie;
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u16 link_sta;
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int ret;
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+ u32 svr;
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pcie = devm_kmalloc(dev, sizeof(*pcie), GFP_KERNEL);
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if (!pcie)
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@@ -191,6 +225,13 @@ static int ls_pcie_ep_probe(struct udevice *dev)
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pcie->big_endian = fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev),
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"big-endian");
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+ svr = SVR_SOC_VER(get_svr());
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+
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+ if (svr == SVR_LS2080A || svr == SVR_LS2085A)
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+ pcie_ep->cfg2_flag = 1;
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+ else
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+ pcie_ep->cfg2_flag = 0;
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+
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pcie->mode = readb(pcie->dbi + PCI_HEADER_TYPE) & 0x7f;
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if (pcie->mode != PCI_HEADER_TYPE_NORMAL)
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return 0;
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