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@@ -6,6 +6,7 @@
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#include <common.h>
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#include <dm.h>
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+#include <fsl_lpuart.h>
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#include <watchdog.h>
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#include <asm/io.h>
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#include <serial.h>
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@@ -48,14 +49,56 @@
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DECLARE_GLOBAL_DATA_PTR;
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+#define LPUART_FLAG_REGMAP_32BIT_REG BIT(0)
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+#define LPUART_FLAG_REGMAP_ENDIAN_BIG BIT(1)
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+
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struct lpuart_serial_platdata {
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- struct lpuart_fsl *reg;
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+ void *reg;
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+ ulong flags;
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};
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-#ifndef CONFIG_LPUART_32B_REG
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-static void _lpuart_serial_setbrg(struct lpuart_fsl *base, int baudrate)
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+static void lpuart_read32(u32 flags, u32 *addr, u32 *val)
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+{
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+ if (flags & LPUART_FLAG_REGMAP_32BIT_REG) {
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+ if (flags & LPUART_FLAG_REGMAP_ENDIAN_BIG)
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+ *(u32 *)val = in_be32(addr);
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+ else
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+ *(u32 *)val = in_le32(addr);
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+ }
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+}
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+
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+static void lpuart_write32(u32 flags, u32 *addr, u32 val)
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+{
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+ if (flags & LPUART_FLAG_REGMAP_32BIT_REG) {
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+ if (flags & LPUART_FLAG_REGMAP_ENDIAN_BIG)
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+ out_be32(addr, val);
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+ else
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+ out_le32(addr, val);
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+ }
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+}
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+
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+
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+#ifndef CONFIG_SYS_CLK_FREQ
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+#define CONFIG_SYS_CLK_FREQ 0
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+#endif
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+
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+u32 __weak get_lpuart_clk(void)
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{
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- u32 clk = mxc_get_clock(MXC_UART_CLK);
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+ return CONFIG_SYS_CLK_FREQ;
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+}
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+
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+static bool is_lpuart32(struct udevice *dev)
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+{
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+ struct lpuart_serial_platdata *plat = dev->platdata;
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+
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+ return plat->flags & LPUART_FLAG_REGMAP_32BIT_REG;
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+}
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+
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+static void _lpuart_serial_setbrg(struct lpuart_serial_platdata *plat,
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+ int baudrate)
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+{
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+ struct lpuart_fsl *base = plat->reg;
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+ u32 clk = get_lpuart_clk();
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u16 sbr;
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sbr = (u16)(clk / (16 * baudrate));
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@@ -65,8 +108,9 @@ static void _lpuart_serial_setbrg(struct lpuart_fsl *base, int baudrate)
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__raw_writeb(sbr & 0xff, &base->ubdl);
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}
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-static int _lpuart_serial_getc(struct lpuart_fsl *base)
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+static int _lpuart_serial_getc(struct lpuart_serial_platdata *plat)
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{
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+ struct lpuart_fsl *base = plat->reg;
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while (!(__raw_readb(&base->us1) & (US1_RDRF | US1_OR)))
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WATCHDOG_RESET();
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@@ -75,8 +119,11 @@ static int _lpuart_serial_getc(struct lpuart_fsl *base)
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return __raw_readb(&base->ud);
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}
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-static void _lpuart_serial_putc(struct lpuart_fsl *base, const char c)
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+static void _lpuart_serial_putc(struct lpuart_serial_platdata *plat,
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+ const char c)
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{
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+ struct lpuart_fsl *base = plat->reg;
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+
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while (!(__raw_readb(&base->us1) & US1_TDRE))
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WATCHDOG_RESET();
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@@ -84,8 +131,10 @@ static void _lpuart_serial_putc(struct lpuart_fsl *base, const char c)
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}
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/* Test whether a character is in the RX buffer */
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-static int _lpuart_serial_tstc(struct lpuart_fsl *base)
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+static int _lpuart_serial_tstc(struct lpuart_serial_platdata *plat)
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{
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+ struct lpuart_fsl *base = plat->reg;
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+
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if (__raw_readb(&base->urcfifo) == 0)
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return 0;
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@@ -96,8 +145,9 @@ static int _lpuart_serial_tstc(struct lpuart_fsl *base)
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* Initialise the serial port with the given baudrate. The settings
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* are always 8 data bits, no parity, 1 stop bit, no start bits.
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*/
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-static int _lpuart_serial_init(struct lpuart_fsl *base)
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+static int _lpuart_serial_init(struct lpuart_serial_platdata *plat)
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{
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+ struct lpuart_fsl *base = (struct lpuart_fsl *)plat->reg;
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u8 ctrl;
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ctrl = __raw_readb(&base->uc2);
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@@ -115,101 +165,71 @@ static int _lpuart_serial_init(struct lpuart_fsl *base)
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__raw_writeb(CFIFO_TXFLUSH | CFIFO_RXFLUSH, &base->ucfifo);
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/* provide data bits, parity, stop bit, etc */
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- _lpuart_serial_setbrg(base, gd->baudrate);
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+ _lpuart_serial_setbrg(plat, gd->baudrate);
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__raw_writeb(UC2_RE | UC2_TE, &base->uc2);
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return 0;
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}
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-static int lpuart_serial_setbrg(struct udevice *dev, int baudrate)
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-{
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- struct lpuart_serial_platdata *plat = dev->platdata;
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- struct lpuart_fsl *reg = plat->reg;
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-
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- _lpuart_serial_setbrg(reg, baudrate);
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-
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- return 0;
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-}
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-
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-static int lpuart_serial_getc(struct udevice *dev)
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-{
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- struct lpuart_serial_platdata *plat = dev->platdata;
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- struct lpuart_fsl *reg = plat->reg;
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-
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- return _lpuart_serial_getc(reg);
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-}
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-
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-static int lpuart_serial_putc(struct udevice *dev, const char c)
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-{
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- struct lpuart_serial_platdata *plat = dev->platdata;
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- struct lpuart_fsl *reg = plat->reg;
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-
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- _lpuart_serial_putc(reg, c);
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-
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- return 0;
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-}
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-
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-static int lpuart_serial_pending(struct udevice *dev, bool input)
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-{
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- struct lpuart_serial_platdata *plat = dev->platdata;
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- struct lpuart_fsl *reg = plat->reg;
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-
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- if (input)
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- return _lpuart_serial_tstc(reg);
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- else
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- return __raw_readb(®->us1) & US1_TDRE ? 0 : 1;
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-}
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-
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-static int lpuart_serial_probe(struct udevice *dev)
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-{
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- struct lpuart_serial_platdata *plat = dev->platdata;
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- struct lpuart_fsl *reg = plat->reg;
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-
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- return _lpuart_serial_init(reg);
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-}
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-#else
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-
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-u32 __weak get_lpuart_clk(void)
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-{
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- return CONFIG_SYS_CLK_FREQ;
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-}
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-
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-static void _lpuart32_serial_setbrg(struct lpuart_fsl *base, int baudrate)
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+static void _lpuart32_serial_setbrg(struct lpuart_serial_platdata *plat,
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+ int baudrate)
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{
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+ struct lpuart_fsl_reg32 *base = plat->reg;
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u32 clk = get_lpuart_clk();
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u32 sbr;
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sbr = (clk / (16 * baudrate));
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/* place adjustment later - n/32 BRFA */
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- out_be32(&base->baud, sbr);
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+ lpuart_write32(plat->flags, &base->baud, sbr);
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}
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-static int _lpuart32_serial_getc(struct lpuart_fsl *base)
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+static int _lpuart32_serial_getc(struct lpuart_serial_platdata *plat)
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{
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+ struct lpuart_fsl_reg32 *base = plat->reg;
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u32 stat;
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- while (((stat = in_be32(&base->stat)) & STAT_RDRF) == 0) {
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- out_be32(&base->stat, STAT_FLAGS);
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+ lpuart_read32(plat->flags, &base->stat, &stat);
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+ while ((stat & STAT_RDRF) == 0) {
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+ lpuart_write32(plat->flags, &base->stat, STAT_FLAGS);
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WATCHDOG_RESET();
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+ lpuart_read32(plat->flags, &base->stat, &stat);
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}
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- return in_be32(&base->data) & 0x3ff;
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+ /* Reuse stat */
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+ lpuart_read32(plat->flags, &base->data, &stat);
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+
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+ return stat & 0x3ff;
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}
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-static void _lpuart32_serial_putc(struct lpuart_fsl *base, const char c)
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+static void _lpuart32_serial_putc(struct lpuart_serial_platdata *plat,
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+ const char c)
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{
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- while (!(in_be32(&base->stat) & STAT_TDRE))
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+ struct lpuart_fsl_reg32 *base = plat->reg;
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+ u32 stat;
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+
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+ while (true) {
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+ lpuart_read32(plat->flags, &base->stat, &stat);
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+
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+ if ((stat & STAT_TDRE))
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+ break;
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+
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WATCHDOG_RESET();
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+ }
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- out_be32(&base->data, c);
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+ lpuart_write32(plat->flags, &base->data, c);
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}
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/* Test whether a character is in the RX buffer */
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-static int _lpuart32_serial_tstc(struct lpuart_fsl *base)
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+static int _lpuart32_serial_tstc(struct lpuart_serial_platdata *plat)
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{
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- if ((in_be32(&base->water) >> 24) == 0)
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+ struct lpuart_fsl_reg32 *base = plat->reg;
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+ u32 water;
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+
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+ lpuart_read32(plat->flags, &base->water, &water);
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+
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+ if ((water >> 24) == 0)
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return 0;
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return 1;
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@@ -219,75 +239,94 @@ static int _lpuart32_serial_tstc(struct lpuart_fsl *base)
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* Initialise the serial port with the given baudrate. The settings
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* are always 8 data bits, no parity, 1 stop bit, no start bits.
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*/
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-static int _lpuart32_serial_init(struct lpuart_fsl *base)
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+static int _lpuart32_serial_init(struct lpuart_serial_platdata *plat)
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{
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- u8 ctrl;
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+ struct lpuart_fsl_reg32 *base = (struct lpuart_fsl_reg32 *)plat->reg;
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+ u32 ctrl;
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- ctrl = in_be32(&base->ctrl);
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+ lpuart_read32(plat->flags, &base->ctrl, &ctrl);
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ctrl &= ~CTRL_RE;
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ctrl &= ~CTRL_TE;
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- out_be32(&base->ctrl, ctrl);
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+ lpuart_write32(plat->flags, &base->ctrl, ctrl);
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- out_be32(&base->modir, 0);
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- out_be32(&base->fifo, ~(FIFO_TXFE | FIFO_RXFE));
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+ lpuart_write32(plat->flags, &base->modir, 0);
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+ lpuart_write32(plat->flags, &base->fifo, ~(FIFO_TXFE | FIFO_RXFE));
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- out_be32(&base->match, 0);
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+ lpuart_write32(plat->flags, &base->match, 0);
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/* provide data bits, parity, stop bit, etc */
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- _lpuart32_serial_setbrg(base, gd->baudrate);
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+ _lpuart32_serial_setbrg(plat, gd->baudrate);
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- out_be32(&base->ctrl, CTRL_RE | CTRL_TE);
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+ lpuart_write32(plat->flags, &base->ctrl, CTRL_RE | CTRL_TE);
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return 0;
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}
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-static int lpuart32_serial_setbrg(struct udevice *dev, int baudrate)
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+static int lpuart_serial_setbrg(struct udevice *dev, int baudrate)
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{
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struct lpuart_serial_platdata *plat = dev->platdata;
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- struct lpuart_fsl *reg = plat->reg;
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- _lpuart32_serial_setbrg(reg, baudrate);
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+ if (is_lpuart32(dev))
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+ _lpuart32_serial_setbrg(plat, baudrate);
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+ else
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+ _lpuart_serial_setbrg(plat, baudrate);
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return 0;
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}
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-static int lpuart32_serial_getc(struct udevice *dev)
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+static int lpuart_serial_getc(struct udevice *dev)
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{
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struct lpuart_serial_platdata *plat = dev->platdata;
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- struct lpuart_fsl *reg = plat->reg;
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- return _lpuart32_serial_getc(reg);
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+ if (is_lpuart32(dev))
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+ return _lpuart32_serial_getc(plat);
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+
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+ return _lpuart_serial_getc(plat);
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}
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-static int lpuart32_serial_putc(struct udevice *dev, const char c)
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+static int lpuart_serial_putc(struct udevice *dev, const char c)
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{
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struct lpuart_serial_platdata *plat = dev->platdata;
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- struct lpuart_fsl *reg = plat->reg;
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- _lpuart32_serial_putc(reg, c);
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+ if (is_lpuart32(dev))
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+ _lpuart32_serial_putc(plat, c);
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+ else
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+ _lpuart_serial_putc(plat, c);
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return 0;
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}
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-static int lpuart32_serial_pending(struct udevice *dev, bool input)
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+static int lpuart_serial_pending(struct udevice *dev, bool input)
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{
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struct lpuart_serial_platdata *plat = dev->platdata;
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struct lpuart_fsl *reg = plat->reg;
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+ struct lpuart_fsl_reg32 *reg32 = plat->reg;
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+ u32 stat;
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+
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+ if (is_lpuart32(dev)) {
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+ if (input) {
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+ return _lpuart32_serial_tstc(plat);
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+ } else {
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+ lpuart_read32(plat->flags, ®32->stat, &stat);
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+ return stat & STAT_TDRE ? 0 : 1;
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+ }
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+ }
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if (input)
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- return _lpuart32_serial_tstc(reg);
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+ return _lpuart_serial_tstc(plat);
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else
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- return in_be32(®->stat) & STAT_TDRE ? 0 : 1;
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+ return __raw_readb(®->us1) & US1_TDRE ? 0 : 1;
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}
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-static int lpuart32_serial_probe(struct udevice *dev)
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+static int lpuart_serial_probe(struct udevice *dev)
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{
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struct lpuart_serial_platdata *plat = dev->platdata;
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- struct lpuart_fsl *reg = plat->reg;
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- return _lpuart32_serial_init(reg);
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+ if (is_lpuart32(dev))
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+ return _lpuart32_serial_init(plat);
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+ else
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+ return _lpuart_serial_init(plat);
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}
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-#endif /* CONFIG_LPUART_32B_REG */
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static int lpuart_serial_ofdata_to_platdata(struct udevice *dev)
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{
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@@ -298,12 +337,12 @@ static int lpuart_serial_ofdata_to_platdata(struct udevice *dev)
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if (addr == FDT_ADDR_T_NONE)
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return -EINVAL;
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- plat->reg = (struct lpuart_fsl *)addr;
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+ plat->reg = (void *)addr;
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+ plat->flags = dev_get_driver_data(dev);
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return 0;
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}
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-#ifndef CONFIG_LPUART_32B_REG
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static const struct dm_serial_ops lpuart_serial_ops = {
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.putc = lpuart_serial_putc,
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.pending = lpuart_serial_pending,
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@@ -312,7 +351,9 @@ static const struct dm_serial_ops lpuart_serial_ops = {
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};
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static const struct udevice_id lpuart_serial_ids[] = {
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- { .compatible = "fsl,vf610-lpuart" },
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+ { .compatible = "fsl,ls1021a-lpuart", .data =
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+ LPUART_FLAG_REGMAP_32BIT_REG | LPUART_FLAG_REGMAP_ENDIAN_BIG },
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+ { .compatible = "fsl,vf610-lpuart"},
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{ }
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};
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@@ -326,27 +367,3 @@ U_BOOT_DRIVER(serial_lpuart) = {
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.ops = &lpuart_serial_ops,
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.flags = DM_FLAG_PRE_RELOC,
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};
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-#else /* CONFIG_LPUART_32B_REG */
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-static const struct dm_serial_ops lpuart32_serial_ops = {
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- .putc = lpuart32_serial_putc,
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- .pending = lpuart32_serial_pending,
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- .getc = lpuart32_serial_getc,
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- .setbrg = lpuart32_serial_setbrg,
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-};
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-
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-static const struct udevice_id lpuart32_serial_ids[] = {
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- { .compatible = "fsl,ls1021a-lpuart" },
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- { }
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-};
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-
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-U_BOOT_DRIVER(serial_lpuart32) = {
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- .name = "serial_lpuart32",
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- .id = UCLASS_SERIAL,
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- .of_match = lpuart32_serial_ids,
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- .ofdata_to_platdata = lpuart_serial_ofdata_to_platdata,
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- .platdata_auto_alloc_size = sizeof(struct lpuart_serial_platdata),
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- .probe = lpuart32_serial_probe,
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- .ops = &lpuart32_serial_ops,
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- .flags = DM_FLAG_PRE_RELOC,
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-};
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-#endif /* CONFIG_LPUART_32B_REG */
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