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@@ -13,6 +13,7 @@
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#include <asm/arch/crm_regs.h>
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#include <asm/arch/mx7-ddr.h>
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#include <common.h>
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+#include <linux/delay.h>
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/*
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* Routine: mx7_dram_cfg
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@@ -37,8 +38,23 @@ void mx7_dram_cfg(struct ddrc *ddrc_regs_val, struct ddrc_mp *ddrc_mp_val,
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(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
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int i;
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- /* Assert DDR Controller preset and DDR PHY reset */
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- writel(SRC_DDRC_RCR_DDRC_CORE_RST_MASK, &src_regs->ddrc_rcr);
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+ /*
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+ * iMX7D RM 9.2.4.9.3 Power removal flow Table 9-11. Re-enabling power
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+ * row 2 says "Reset controller / PHY by driving core_ddrc_rst = 0 ,
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+ * aresetn_n = 0, presetn = 0. That means reset everything.
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+ */
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+ writel(SRC_DDRC_RCR_DDRC_CORE_RST_MASK | SRC_DDRC_RCR_DDRC_PRST_MASK,
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+ &src_regs->ddrc_rcr);
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+
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+ /*
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+ * iMX7D RM 6.2.7.26 SRC_DDRC_RCR says wait 30 cycles (of unknown).
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+ * If we assume this is 30 cycles at 100 MHz (about the rate of a
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+ * DRAM bus), that's 300 nS, so waiting 10 uS is more then plenty.
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+ */
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+ udelay(10);
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+
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+ /* De-assert DDR Controller 'preset' and DDR PHY reset */
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+ clrbits_le32(&src_regs->ddrc_rcr, SRC_DDRC_RCR_DDRC_PRST_MASK);
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/* DDR controller configuration */
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writel(ddrc_regs_val->mstr, &ddrc_regs->mstr);
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@@ -71,7 +87,7 @@ void mx7_dram_cfg(struct ddrc *ddrc_regs_val, struct ddrc_mp *ddrc_mp_val,
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writel(ddrc_regs_val->odtcfg, &ddrc_regs->odtcfg);
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writel(ddrc_regs_val->odtmap, &ddrc_regs->odtmap);
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- /* De-assert DDR Controller preset and DDR PHY reset */
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+ /* De-assert DDR Controller 'core_ddrc_rstn' and 'aresetn' */
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clrbits_le32(&src_regs->ddrc_rcr, SRC_DDRC_RCR_DDRC_CORE_RST_MASK);
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/* PHY configuration */
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