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@@ -8,6 +8,7 @@
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#include <log.h>
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#include <misc.h>
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#include <asm/io.h>
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+#include <asm/arch/bsec.h>
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#include <asm/arch/stm32mp1_smc.h>
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#include <linux/arm-smccc.h>
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#include <linux/iopoll.h>
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@@ -21,6 +22,7 @@
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#define BSEC_OTP_WRDATA_OFF 0x008
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#define BSEC_OTP_STATUS_OFF 0x00C
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#define BSEC_OTP_LOCK_OFF 0x010
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+#define BSEC_DENABLE_OFF 0x014
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#define BSEC_DISTURBED_OFF 0x01C
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#define BSEC_ERROR_OFF 0x034
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#define BSEC_WRLOCK_OFF 0x04C /* OTP write permananet lock */
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@@ -46,6 +48,9 @@
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#define BSEC_MODE_PROGFAIL_MASK 0x10
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#define BSEC_MODE_PWR_MASK 0x20
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+/* DENABLE Register */
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+#define BSEC_DENABLE_DBGSWENABLE BIT(10)
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+
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/*
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* OTP Lock services definition
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* Value must corresponding to the bit number in the register
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@@ -506,3 +511,23 @@ U_BOOT_DRIVER(stm32mp_bsec) = {
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.ops = &stm32mp_bsec_ops,
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.probe = stm32mp_bsec_probe,
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};
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+
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+bool bsec_dbgswenable(void)
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+{
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+ struct udevice *dev;
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+ struct stm32mp_bsec_platdata *plat;
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+ int ret;
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+
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+ ret = uclass_get_device_by_driver(UCLASS_MISC,
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+ DM_GET_DRIVER(stm32mp_bsec), &dev);
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+ if (ret || !dev) {
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+ pr_debug("bsec driver not available\n");
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+ return false;
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+ }
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+
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+ plat = dev_get_platdata(dev);
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+ if (readl(plat->base + BSEC_DENABLE_OFF) & BSEC_DENABLE_DBGSWENABLE)
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+ return true;
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+
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+ return false;
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+}
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