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@@ -15,8 +15,6 @@
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DECLARE_GLOBAL_DATA_PTR;
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-static const struct socfpga_reset_manager *reset_manager_base =
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- (void *)SOCFPGA_RSTMGR_ADDRESS;
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static const struct socfpga_system_manager *sysmgr_regs =
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(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
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@@ -63,14 +61,14 @@ static const struct bridge_cfg bridge_cfg_tbl[] = {
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void socfpga_watchdog_disable(void)
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{
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/* assert reset for watchdog */
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- setbits_le32(&reset_manager_base->per1modrst,
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+ setbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_A10_PER1MODRST,
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ALT_RSTMGR_PER1MODRST_WD0_SET_MSK);
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}
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/* Release NOC ddr scheduler from reset */
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void socfpga_reset_deassert_noc_ddr_scheduler(void)
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{
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- clrbits_le32(&reset_manager_base->brgmodrst,
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+ clrbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_A10_BRGMODRST,
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ALT_RSTMGR_BRGMODRST_DDRSCH_SET_MSK);
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}
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@@ -103,7 +101,8 @@ int socfpga_reset_deassert_bridges_handoff(void)
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setbits_le32(&sysmgr_regs->noc_idlereq_clr, mask_noc);
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/* Release bridges from reset state per handoff value */
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- clrbits_le32(&reset_manager_base->brgmodrst, mask_rstmgr);
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+ clrbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_A10_BRGMODRST,
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+ mask_rstmgr);
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/* Poll until all idleack to 0, timeout at 1000ms */
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return wait_for_bit_le32(&sysmgr_regs->noc_idleack, mask_noc,
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@@ -113,7 +112,7 @@ int socfpga_reset_deassert_bridges_handoff(void)
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/* Release L4 OSC1 Watchdog Timer 0 from reset through reset manager */
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void socfpga_reset_deassert_osc1wd0(void)
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{
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- clrbits_le32(&reset_manager_base->per1modrst,
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+ clrbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_A10_PER1MODRST,
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ALT_RSTMGR_PER1MODRST_WD0_SET_MSK);
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}
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@@ -122,24 +121,24 @@ void socfpga_reset_deassert_osc1wd0(void)
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*/
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void socfpga_per_reset(u32 reset, int set)
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{
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- const u32 *reg;
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+ unsigned long reg;
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u32 rstmgr_bank = RSTMGR_BANK(reset);
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switch (rstmgr_bank) {
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case 0:
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- reg = &reset_manager_base->mpumodrst;
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+ reg = RSTMGR_A10_MPUMODRST;
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break;
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case 1:
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- reg = &reset_manager_base->per0modrst;
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+ reg = RSTMGR_A10_PER0MODRST;
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break;
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case 2:
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- reg = &reset_manager_base->per1modrst;
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+ reg = RSTMGR_A10_PER1MODRST;
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break;
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case 3:
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- reg = &reset_manager_base->brgmodrst;
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+ reg = RSTMGR_A10_BRGMODRST;
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break;
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case 4:
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- reg = &reset_manager_base->sysmodrst;
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+ reg = RSTMGR_A10_SYSMODRST;
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break;
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default:
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@@ -147,9 +146,11 @@ void socfpga_per_reset(u32 reset, int set)
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}
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if (set)
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- setbits_le32(reg, 1 << RSTMGR_RESET(reset));
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+ setbits_le32(socfpga_get_rstmgr_addr() + reg,
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+ 1 << RSTMGR_RESET(reset));
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else
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- clrbits_le32(reg, 1 << RSTMGR_RESET(reset));
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+ clrbits_le32(socfpga_get_rstmgr_addr() + reg,
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+ 1 << RSTMGR_RESET(reset));
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}
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/*
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@@ -174,11 +175,13 @@ void socfpga_per_reset_all(void)
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ALT_RSTMGR_PER0MODRST_SDMMCECC_SET_MSK;
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/* disable all components except ECC_OCP, L4 Timer0 and L4 WD0 */
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- writel(~l4wd0, &reset_manager_base->per1modrst);
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- setbits_le32(&reset_manager_base->per0modrst, ~mask_ecc_ocp);
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+ writel(~l4wd0, socfpga_get_rstmgr_addr() + RSTMGR_A10_PER1MODRST);
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+ setbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_A10_PER0MODRST,
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+ ~mask_ecc_ocp);
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/* Finally disable the ECC_OCP */
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- setbits_le32(&reset_manager_base->per0modrst, mask_ecc_ocp);
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+ setbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_A10_PER0MODRST,
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+ mask_ecc_ocp);
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}
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int socfpga_bridges_reset(void)
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@@ -224,13 +227,13 @@ int socfpga_bridges_reset(void)
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return ret;
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/* Put all bridges (except NOR DDR scheduler) into reset state */
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- setbits_le32(&reset_manager_base->brgmodrst,
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+ setbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_A10_BRGMODRST,
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(ALT_RSTMGR_BRGMODRST_H2F_SET_MSK |
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- ALT_RSTMGR_BRGMODRST_LWH2F_SET_MSK |
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- ALT_RSTMGR_BRGMODRST_F2H_SET_MSK |
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- ALT_RSTMGR_BRGMODRST_F2SSDRAM0_SET_MSK |
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- ALT_RSTMGR_BRGMODRST_F2SSDRAM1_SET_MSK |
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- ALT_RSTMGR_BRGMODRST_F2SSDRAM2_SET_MSK));
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+ ALT_RSTMGR_BRGMODRST_LWH2F_SET_MSK |
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+ ALT_RSTMGR_BRGMODRST_F2H_SET_MSK |
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+ ALT_RSTMGR_BRGMODRST_F2SSDRAM0_SET_MSK |
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+ ALT_RSTMGR_BRGMODRST_F2SSDRAM1_SET_MSK |
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+ ALT_RSTMGR_BRGMODRST_F2SSDRAM2_SET_MSK));
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/* Disable NOC timeout */
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writel(0, &sysmgr_regs->noc_timeout);
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