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@@ -0,0 +1,156 @@
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+// SPDX-License-Identifier: GPL-2.0+
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+/*
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+ * Master clock support for AT91 architectures.
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+ *
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+ * Copyright (C) 2020 Microchip Technology Inc. and its subsidiaries
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+ *
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+ * Author: Claudiu Beznea <claudiu.beznea@microchip.com>
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+ *
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+ * Based on drivers/clk/at91/clk-master.c from Linux.
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+ */
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+
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+#include <asm/processor.h>
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+#include <clk-uclass.h>
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+#include <common.h>
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+#include <dm.h>
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+#include <linux/clk-provider.h>
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+#include <linux/clk/at91_pmc.h>
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+
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+#include "pmc.h"
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+
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+#define UBOOT_DM_CLK_AT91_MASTER "at91-master-clk"
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+
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+#define MASTER_PRES_MASK 0x7
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+#define MASTER_PRES_MAX MASTER_PRES_MASK
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+#define MASTER_DIV_SHIFT 8
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+#define MASTER_DIV_MASK 0x3
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+
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+struct clk_master {
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+ void __iomem *base;
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+ const struct clk_master_layout *layout;
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+ const struct clk_master_characteristics *characteristics;
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+ const u32 *mux_table;
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+ const u32 *clk_mux_table;
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+ u32 num_parents;
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+ struct clk clk;
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+ u8 id;
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+};
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+
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+#define to_clk_master(_clk) container_of(_clk, struct clk_master, clk)
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+
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+static inline bool clk_master_ready(struct clk_master *master)
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+{
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+ unsigned int status;
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+
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+ pmc_read(master->base, AT91_PMC_SR, &status);
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+
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+ return !!(status & AT91_PMC_MCKRDY);
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+}
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+
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+static int clk_master_enable(struct clk *clk)
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+{
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+ struct clk_master *master = to_clk_master(clk);
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+
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+ while (!clk_master_ready(master)) {
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+ debug("waiting for mck %d\n", master->id);
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+ cpu_relax();
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+ }
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+
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+ return 0;
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+}
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+
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+static ulong clk_master_get_rate(struct clk *clk)
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+{
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+ struct clk_master *master = to_clk_master(clk);
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+ const struct clk_master_layout *layout = master->layout;
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+ const struct clk_master_characteristics *characteristics =
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+ master->characteristics;
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+ ulong rate = clk_get_parent_rate(clk);
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+ unsigned int mckr;
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+ u8 pres, div;
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+
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+ if (!rate)
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+ return 0;
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+
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+ pmc_read(master->base, master->layout->offset, &mckr);
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+ mckr &= layout->mask;
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+
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+ pres = (mckr >> layout->pres_shift) & MASTER_PRES_MASK;
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+ div = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK;
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+
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+ if (characteristics->have_div3_pres && pres == MASTER_PRES_MAX)
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+ rate /= 3;
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+ else
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+ rate >>= pres;
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+
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+ rate /= characteristics->divisors[div];
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+
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+ if (rate < characteristics->output.min)
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+ pr_warn("master clk is underclocked");
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+ else if (rate > characteristics->output.max)
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+ pr_warn("master clk is overclocked");
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+
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+ return rate;
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+}
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+
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+static const struct clk_ops master_ops = {
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+ .enable = clk_master_enable,
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+ .get_rate = clk_master_get_rate,
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+};
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+
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+struct clk *at91_clk_register_master(void __iomem *base,
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+ const char *name, const char * const *parent_names,
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+ int num_parents, const struct clk_master_layout *layout,
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+ const struct clk_master_characteristics *characteristics,
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+ const u32 *mux_table)
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+{
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+ struct clk_master *master;
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+ struct clk *clk;
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+ unsigned int val;
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+ int ret;
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+
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+ if (!base || !name || !num_parents || !parent_names ||
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+ !layout || !characteristics || !mux_table)
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+ return ERR_PTR(-EINVAL);
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+
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+ master = kzalloc(sizeof(*master), GFP_KERNEL);
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+ if (!master)
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+ return ERR_PTR(-ENOMEM);
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+
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+ master->layout = layout;
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+ master->characteristics = characteristics;
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+ master->base = base;
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+ master->num_parents = num_parents;
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+ master->mux_table = mux_table;
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+
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+ pmc_read(master->base, master->layout->offset, &val);
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+ clk = &master->clk;
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+ clk->flags = CLK_GET_RATE_NOCACHE | CLK_IS_CRITICAL;
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+ ret = clk_register(clk, UBOOT_DM_CLK_AT91_MASTER, name,
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+ parent_names[val & AT91_PMC_CSS]);
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+ if (ret) {
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+ kfree(master);
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+ clk = ERR_PTR(ret);
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+ }
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+
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+ return clk;
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+}
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+
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+U_BOOT_DRIVER(at91_master_clk) = {
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+ .name = UBOOT_DM_CLK_AT91_MASTER,
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+ .id = UCLASS_CLK,
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+ .ops = &master_ops,
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+ .flags = DM_FLAG_PRE_RELOC,
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+};
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+
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+const struct clk_master_layout at91rm9200_master_layout = {
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+ .mask = 0x31F,
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+ .pres_shift = 2,
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+ .offset = AT91_PMC_MCKR,
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+};
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+
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+const struct clk_master_layout at91sam9x5_master_layout = {
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+ .mask = 0x373,
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+ .pres_shift = 4,
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+ .offset = AT91_PMC_MCKR,
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+};
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