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@@ -2,7 +2,7 @@
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/*
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* NVIDIA Tegra210 QSPI controller driver
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*
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- * (C) Copyright 2015-2019 NVIDIA Corporation <www.nvidia.com>
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+ * (C) Copyright 2015-2020 NVIDIA Corporation <www.nvidia.com>
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*
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*/
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@@ -97,10 +97,8 @@ struct tegra210_qspi_priv {
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static int tegra210_qspi_ofdata_to_platdata(struct udevice *bus)
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{
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struct tegra_spi_platdata *plat = bus->platdata;
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- const void *blob = gd->fdt_blob;
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- int node = dev_of_offset(bus);
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- plat->base = devfdt_get_addr(bus);
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+ plat->base = dev_read_addr(bus);
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plat->periph_id = clock_decode_periph_id(bus);
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if (plat->periph_id == PERIPH_ID_NONE) {
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@@ -110,10 +108,11 @@ static int tegra210_qspi_ofdata_to_platdata(struct udevice *bus)
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}
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/* Use 500KHz as a suitable default */
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- plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
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- 500000);
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- plat->deactivate_delay_us = fdtdec_get_int(blob, node,
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- "spi-deactivate-delay", 0);
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+ plat->frequency = dev_read_u32_default(bus, "spi-max-frequency",
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+ 500000);
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+ plat->deactivate_delay_us = dev_read_u32_default(bus,
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+ "spi-deactivate-delay",
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+ 0);
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debug("%s: base=%#08lx, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n",
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__func__, plat->base, plat->periph_id, plat->frequency,
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plat->deactivate_delay_us);
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