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@@ -0,0 +1,165 @@
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+// SPDX-License-Identifier: GPL-2.0+
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+/*
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+ * UTMI clock support for AT91 architectures.
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+ *
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+ * Copyright (C) 2020 Microchip Technology Inc. and its subsidiaries
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+ *
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+ * Author: Claudiu Beznea <claudiu.beznea@microchip.com>
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+ *
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+ * Based on drivers/clk/at91/clk-utmi.c from Linux.
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+ */
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+#include <asm/processor.h>
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+#include <common.h>
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+#include <clk-uclass.h>
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+#include <dm.h>
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+#include <linux/clk-provider.h>
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+#include <linux/clk/at91_pmc.h>
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+#include <mach/at91_sfr.h>
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+#include <regmap.h>
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+#include <syscon.h>
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+
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+#include "pmc.h"
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+
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+#define UBOOT_DM_CLK_AT91_UTMI "at91-utmi-clk"
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+
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+/*
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+ * The purpose of this clock is to generate a 480 MHz signal. A different
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+ * rate can't be configured.
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+ */
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+#define UTMI_RATE 480000000
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+
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+struct clk_utmi {
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+ void __iomem *base;
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+ struct regmap *regmap_sfr;
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+ struct clk clk;
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+};
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+
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+#define to_clk_utmi(_clk) container_of(_clk, struct clk_utmi, clk)
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+
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+static inline bool clk_utmi_ready(struct regmap *regmap)
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+{
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+ unsigned int status;
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+
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+ pmc_read(regmap, AT91_PMC_SR, &status);
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+
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+ return !!(status & AT91_PMC_LOCKU);
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+}
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+
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+static int clk_utmi_enable(struct clk *clk)
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+{
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+ struct clk_utmi *utmi = to_clk_utmi(clk);
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+ unsigned int uckr = AT91_PMC_UPLLEN | AT91_PMC_UPLLCOUNT |
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+ AT91_PMC_BIASEN;
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+ unsigned int utmi_ref_clk_freq;
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+ ulong parent_rate = clk_get_parent_rate(clk);
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+
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+ /*
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+ * If mainck rate is different from 12 MHz, we have to configure the
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+ * FREQ field of the SFR_UTMICKTRIM register to generate properly
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+ * the utmi clock.
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+ */
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+ switch (parent_rate) {
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+ case 12000000:
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+ utmi_ref_clk_freq = 0;
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+ break;
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+ case 16000000:
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+ utmi_ref_clk_freq = 1;
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+ break;
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+ case 24000000:
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+ utmi_ref_clk_freq = 2;
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+ break;
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+ /*
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+ * Not supported on SAMA5D2 but it's not an issue since MAINCK
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+ * maximum value is 24 MHz.
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+ */
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+ case 48000000:
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+ utmi_ref_clk_freq = 3;
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+ break;
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+ default:
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+ debug("UTMICK: unsupported mainck rate\n");
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+ return -EINVAL;
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+ }
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+
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+ if (utmi->regmap_sfr) {
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+ regmap_update_bits(utmi->regmap_sfr, AT91_SFR_UTMICKTRIM,
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+ AT91_UTMICKTRIM_FREQ, utmi_ref_clk_freq);
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+ } else if (utmi_ref_clk_freq) {
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+ debug("UTMICK: sfr node required\n");
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+ return -EINVAL;
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+ }
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+
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+ pmc_update_bits(utmi->base, AT91_CKGR_UCKR, uckr, uckr);
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+
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+ while (!clk_utmi_ready(utmi->base)) {
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+ debug("waiting for utmi...\n");
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+ cpu_relax();
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+ }
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+
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+ return 0;
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+}
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+
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+static int clk_utmi_disable(struct clk *clk)
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+{
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+ struct clk_utmi *utmi = to_clk_utmi(clk);
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+
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+ pmc_update_bits(utmi->base, AT91_CKGR_UCKR, AT91_PMC_UPLLEN, 0);
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+
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+ return 0;
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+}
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+
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+static ulong clk_utmi_get_rate(struct clk *clk)
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+{
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+ /* UTMI clk rate is fixed. */
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+ return UTMI_RATE;
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+}
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+
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+static const struct clk_ops utmi_ops = {
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+ .enable = clk_utmi_enable,
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+ .disable = clk_utmi_disable,
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+ .get_rate = clk_utmi_get_rate,
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+};
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+
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+struct clk *at91_clk_register_utmi(void __iomem *base, struct udevice *dev,
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+ const char *name, const char *parent_name)
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+{
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+ struct udevice *syscon;
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+ struct clk_utmi *utmi;
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+ struct clk *clk;
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+ int ret;
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+
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+ if (!base || !dev || !name || !parent_name)
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+ return ERR_PTR(-EINVAL);
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+
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+ ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev,
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+ "regmap-sfr", &syscon);
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+ if (ret)
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+ return ERR_PTR(ret);
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+
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+ utmi = kzalloc(sizeof(*utmi), GFP_KERNEL);
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+ if (!utmi)
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+ return ERR_PTR(-ENOMEM);
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+
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+ utmi->base = base;
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+ utmi->regmap_sfr = syscon_get_regmap(syscon);
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+ if (!utmi->regmap_sfr) {
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+ kfree(utmi);
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+ return ERR_PTR(-ENODEV);
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+ }
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+
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+ clk = &utmi->clk;
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+ clk->flags = CLK_GET_RATE_NOCACHE;
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+ ret = clk_register(clk, UBOOT_DM_CLK_AT91_UTMI, name, parent_name);
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+ if (ret) {
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+ kfree(utmi);
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+ clk = ERR_PTR(ret);
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+ }
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+
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+ return clk;
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+}
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+
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+U_BOOT_DRIVER(at91_utmi_clk) = {
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+ .name = UBOOT_DM_CLK_AT91_UTMI,
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+ .id = UCLASS_CLK,
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+ .ops = &utmi_ops,
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+ .flags = DM_FLAG_PRE_RELOC,
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+};
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