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@@ -1328,23 +1328,38 @@
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dma-requests = <48>;
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};
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- fmc: nand-controller@58002000 {
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- compatible = "st,stm32mp15-fmc2";
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- reg = <0x58002000 0x1000>,
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- <0x80000000 0x1000>,
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- <0x88010000 0x1000>,
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- <0x88020000 0x1000>,
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- <0x81000000 0x1000>,
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- <0x89010000 0x1000>,
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- <0x89020000 0x1000>;
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- interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
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- dmas = <&mdma1 20 0x10 0x12000a02 0x0 0x0>,
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- <&mdma1 20 0x10 0x12000a08 0x0 0x0>,
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- <&mdma1 21 0x10 0x12000a0a 0x0 0x0>;
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- dma-names = "tx", "rx", "ecc";
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+ fmc: memory-controller@58002000 {
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+ #address-cells = <2>;
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+ #size-cells = <1>;
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+ compatible = "st,stm32mp1-fmc2-ebi";
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+ reg = <0x58002000 0x1000>;
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clocks = <&rcc FMC_K>;
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resets = <&rcc FMC_R>;
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status = "disabled";
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+
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+ ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */
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+ <1 0 0x64000000 0x04000000>, /* EBI CS 2 */
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+ <2 0 0x68000000 0x04000000>, /* EBI CS 3 */
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+ <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */
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+ <4 0 0x80000000 0x10000000>; /* NAND */
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+
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+ nand-controller@4,0 {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ compatible = "st,stm32mp1-fmc2-nfc";
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+ reg = <4 0x00000000 0x1000>,
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+ <4 0x08010000 0x1000>,
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+ <4 0x08020000 0x1000>,
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+ <4 0x01000000 0x1000>,
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+ <4 0x09010000 0x1000>,
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+ <4 0x09020000 0x1000>;
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+ interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
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+ dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0>,
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+ <&mdma1 20 0x2 0x12000a08 0x0 0x0>,
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+ <&mdma1 21 0x2 0x12000a0a 0x0 0x0>;
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+ dma-names = "tx", "rx", "ecc";
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+ status = "disabled";
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+ };
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};
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qspi: spi@58003000 {
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