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@@ -10,15 +10,15 @@
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#include <asm/arch/ns_access.h>
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#include <asm/arch/fsl_serdes.h>
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-void set_devices_ns_access(struct csu_ns_dev *ns_dev, u16 val)
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+void set_devices_ns_access(unsigned long index, u16 val)
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{
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u32 *base = (u32 *)CONFIG_SYS_FSL_CSU_ADDR;
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u32 *reg;
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uint32_t tmp;
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- reg = base + ns_dev->ind / 2;
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+ reg = base + index / 2;
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tmp = in_be32(reg);
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- if (ns_dev->ind % 2 == 0) {
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+ if (index % 2 == 0) {
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tmp &= 0x0000ffff;
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tmp |= val << 16;
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} else {
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@@ -34,7 +34,7 @@ static void enable_devices_ns_access(struct csu_ns_dev *ns_dev, uint32_t num)
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int i;
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for (i = 0; i < num; i++)
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- set_devices_ns_access(ns_dev + i, ns_dev[i].val);
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+ set_devices_ns_access(ns_dev[i].ind, ns_dev[i].val);
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}
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void enable_layerscape_ns_access(void)
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@@ -50,20 +50,20 @@ void set_pcie_ns_access(int pcie, u16 val)
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switch (pcie) {
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#ifdef CONFIG_PCIE1
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case PCIE1:
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- set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE1], val);
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- set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE1_IO], val);
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+ set_devices_ns_access(CSU_CSLX_PCIE1, val);
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+ set_devices_ns_access(CSU_CSLX_PCIE1_IO, val);
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return;
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#endif
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#ifdef CONFIG_PCIE2
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case PCIE2:
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- set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE2], val);
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- set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE2_IO], val);
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+ set_devices_ns_access(CSU_CSLX_PCIE2, val);
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+ set_devices_ns_access(CSU_CSLX_PCIE2_IO, val);
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return;
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#endif
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#ifdef CONFIG_PCIE3
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case PCIE3:
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- set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE3], val);
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- set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE3_IO], val);
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+ set_devices_ns_access(CSU_CSLX_PCIE3, val);
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+ set_devices_ns_access(CSU_CSLX_PCIE3_IO, val);
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return;
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#endif
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default:
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