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@@ -103,8 +103,11 @@ int arch_cpu_init(void)
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&clkctrl_regs->hw_clkctrl_clkseq_set);
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/* Set GPMI clock to ref_xtal / 1 */
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+ clrbits_le32(&clkctrl_regs->hw_clkctrl_gpmi, CLKCTRL_GPMI_CLKGATE);
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+ while (readl(&clkctrl_regs->hw_clkctrl_gpmi) & CLKCTRL_GPMI_CLKGATE)
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+ ;
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clrsetbits_le32(&clkctrl_regs->hw_clkctrl_gpmi,
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- CLKCTRL_GPMI_CLKGATE | CLKCTRL_GPMI_DIV_MASK, 1);
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+ CLKCTRL_GPMI_DIV_MASK, 1);
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udelay(1000);
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