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@@ -1,39 +1,44 @@
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-STM32 QSPI controller device tree bindings
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---------------------------------------------
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+* STMicroelectronics Quad Serial Peripheral Interface(QSPI)
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Required properties:
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-- compatible : should be "st,stm32-qspi".
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-- reg : 1. Physical base address and size of SPI registers map.
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- 2. Physical base address & size of mapped NOR Flash.
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-- spi-max-frequency : Max supported spi frequency.
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-- status : enable in requried dts.
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-
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-Connected flash properties
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---------------------------
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-- spi-max-frequency : Max supported spi frequency.
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-- spi-tx-bus-width : Bus width (number of lines) for writing (1-4)
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-- spi-rx-bus-width : Bus width (number of lines) for reading (1-4)
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-- memory-map : Address and size for memory-mapping the flash
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+- compatible: should be "st,stm32f469-qspi"
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+- reg: the first contains the register location and length.
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+ the second contains the memory mapping address and length
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+- reg-names: should contain the reg names "qspi" "qspi_mm"
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+- interrupts: should contain the interrupt for the device
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+- clocks: the phandle of the clock needed by the QSPI controller
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+- A pinctrl must be defined to set pins in mode of operation for QSPI transfer
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+
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+Optional properties:
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+- resets: must contain the phandle to the reset controller.
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+
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+A spi flash (NOR/NAND) must be a child of spi node and could have some
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+properties. Also see jedec,spi-nor.txt.
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+
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+Required properties:
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+- reg: chip-Select number (QSPI controller may connect 2 flashes)
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+- spi-max-frequency: max frequency of spi bus
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+
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+Optional property:
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+- spi-rx-bus-width: see ./spi-bus.txt for the description
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Example:
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- qspi: quadspi@A0001000 {
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- compatible = "st,stm32-qspi";
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- #address-cells = <1>;
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- #size-cells = <0>;
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- reg = <0xA0001000 0x1000>, <0x90000000 0x10000000>;
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- reg-names = "QuadSPI", "QuadSPI-memory";
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- interrupts = <92>;
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+
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+qspi: spi@a0001000 {
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+ compatible = "st,stm32f469-qspi";
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+ reg = <0xa0001000 0x1000>, <0x90000000 0x10000000>;
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+ reg-names = "qspi", "qspi_mm";
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+ interrupts = <91>;
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+ resets = <&rcc STM32F4_AHB3_RESET(QSPI)>;
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+ clocks = <&rcc 0 STM32F4_AHB3_CLOCK(QSPI)>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&pinctrl_qspi0>;
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+
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+ flash@0 {
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+ compatible = "jedec,spi-nor";
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+ reg = <0>;
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+ spi-rx-bus-width = <4>;
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spi-max-frequency = <108000000>;
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- status = "okay";
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-
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- qflash0: n25q128a {
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- #address-cells = <1>;
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- #size-cells = <1>;
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- compatible = "micron,n25q128a13", "jedec,spi-nor";
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- spi-max-frequency = <108000000>;
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- spi-tx-bus-width = <4>;
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- spi-rx-bus-width = <4>;
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- memory-map = <0x90000000 0x1000000>;
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- reg = <0>;
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- };
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+ ...
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};
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+};
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