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@@ -6,8 +6,11 @@
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/sun50i-h6-ccu.h>
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#include <dt-bindings/clock/sun50i-h6-r-ccu.h>
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+#include <dt-bindings/clock/sun8i-de2.h>
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+#include <dt-bindings/clock/sun8i-tcon-top.h>
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#include <dt-bindings/reset/sun50i-h6-ccu.h>
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#include <dt-bindings/reset/sun50i-h6-r-ccu.h>
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+#include <dt-bindings/reset/sun8i-de2.h>
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/ {
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interrupt-parent = <&gic>;
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@@ -19,34 +22,40 @@
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#size-cells = <0>;
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cpu0: cpu@0 {
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- compatible = "arm,cortex-a53", "arm,armv8";
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+ compatible = "arm,cortex-a53";
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device_type = "cpu";
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reg = <0>;
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enable-method = "psci";
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};
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cpu1: cpu@1 {
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- compatible = "arm,cortex-a53", "arm,armv8";
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+ compatible = "arm,cortex-a53";
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device_type = "cpu";
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reg = <1>;
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enable-method = "psci";
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};
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cpu2: cpu@2 {
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- compatible = "arm,cortex-a53", "arm,armv8";
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+ compatible = "arm,cortex-a53";
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device_type = "cpu";
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reg = <2>;
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enable-method = "psci";
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};
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cpu3: cpu@3 {
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- compatible = "arm,cortex-a53", "arm,armv8";
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+ compatible = "arm,cortex-a53";
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device_type = "cpu";
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reg = <3>;
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enable-method = "psci";
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};
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};
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+ de: display-engine {
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+ compatible = "allwinner,sun50i-h6-display-engine";
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+ allwinner,pipelines = <&mixer0>;
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+ status = "disabled";
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+ };
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+
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iosc: internal-osc-clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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@@ -92,6 +101,99 @@
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#size-cells = <1>;
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ranges;
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+ display-engine@1000000 {
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+ compatible = "allwinner,sun50i-h6-de3",
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+ "allwinner,sun50i-a64-de2";
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+ reg = <0x1000000 0x400000>;
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+ allwinner,sram = <&de2_sram 1>;
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ ranges = <0 0x1000000 0x400000>;
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+
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+ display_clocks: clock@0 {
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+ compatible = "allwinner,sun50i-h6-de3-clk";
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+ reg = <0x0 0x10000>;
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+ clocks = <&ccu CLK_DE>,
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+ <&ccu CLK_BUS_DE>;
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+ clock-names = "mod",
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+ "bus";
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+ resets = <&ccu RST_BUS_DE>;
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+ #clock-cells = <1>;
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+ #reset-cells = <1>;
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+ };
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+
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+ mixer0: mixer@100000 {
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+ compatible = "allwinner,sun50i-h6-de3-mixer-0";
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+ reg = <0x100000 0x100000>;
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+ clocks = <&display_clocks CLK_BUS_MIXER0>,
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+ <&display_clocks CLK_MIXER0>;
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+ clock-names = "bus",
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+ "mod";
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+ resets = <&display_clocks RST_MIXER0>;
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+
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+ ports {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ mixer0_out: port@1 {
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+ reg = <1>;
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+
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+ mixer0_out_tcon_top_mixer0: endpoint {
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+ remote-endpoint = <&tcon_top_mixer0_in_mixer0>;
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+ };
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+ };
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+ };
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+ };
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+ };
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+
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+ video-codec@1c0e000 {
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+ compatible = "allwinner,sun50i-h6-video-engine";
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+ reg = <0x01c0e000 0x2000>;
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+ clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
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+ <&ccu CLK_MBUS_VE>;
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+ clock-names = "ahb", "mod", "ram";
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+ resets = <&ccu RST_BUS_VE>;
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+ interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
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+ allwinner,sram = <&ve_sram 1>;
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+ };
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+
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+ syscon: syscon@3000000 {
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+ compatible = "allwinner,sun50i-h6-system-control",
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+ "allwinner,sun50i-a64-system-control";
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+ reg = <0x03000000 0x1000>;
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ ranges;
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+
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+ sram_c: sram@28000 {
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+ compatible = "mmio-sram";
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+ reg = <0x00028000 0x1e000>;
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ ranges = <0 0x00028000 0x1e000>;
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+
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+ de2_sram: sram-section@0 {
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+ compatible = "allwinner,sun50i-h6-sram-c",
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+ "allwinner,sun50i-a64-sram-c";
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+ reg = <0x0000 0x1e000>;
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+ };
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+ };
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+
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+ sram_c1: sram@1a00000 {
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+ compatible = "mmio-sram";
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+ reg = <0x01a00000 0x200000>;
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ ranges = <0 0x01a00000 0x200000>;
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+
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+ ve_sram: sram-section@0 {
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+ compatible = "allwinner,sun50i-h6-sram-c1",
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+ "allwinner,sun4i-a10-sram-c1";
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+ reg = <0x000000 0x200000>;
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+ };
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+ };
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+ };
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+
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ccu: clock@3001000 {
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compatible = "allwinner,sun50i-h6-ccu";
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reg = <0x03001000 0x1000>;
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@@ -101,15 +203,9 @@
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#reset-cells = <1>;
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};
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- gic: interrupt-controller@3021000 {
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- compatible = "arm,gic-400";
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- reg = <0x03021000 0x1000>,
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- <0x03022000 0x2000>,
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- <0x03024000 0x2000>,
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- <0x03026000 0x2000>;
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- interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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- interrupt-controller;
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- #interrupt-cells = <3>;
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+ sid: sid@3006000 {
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+ compatible = "allwinner,sun50i-h6-sid";
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+ reg = <0x03006000 0x400>;
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};
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pio: pinctrl@300b000 {
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@@ -126,6 +222,19 @@
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interrupt-controller;
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#interrupt-cells = <3>;
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+ ext_rgmii_pins: rgmii-pins {
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+ pins = "PD0", "PD1", "PD2", "PD3", "PD4",
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+ "PD5", "PD7", "PD8", "PD9", "PD10",
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+ "PD11", "PD12", "PD13", "PD19", "PD20";
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+ function = "emac";
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+ drive-strength = <40>;
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+ };
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+
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+ hdmi_pins: hdmi-pins {
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+ pins = "PH8", "PH9", "PH10";
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+ function = "hdmi";
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+ };
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+
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mmc0_pins: mmc0-pins {
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pins = "PF0", "PF1", "PF2", "PF3",
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"PF4", "PF5";
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@@ -143,12 +252,23 @@
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bias-pull-up;
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};
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- uart0_ph_pins: uart0-ph {
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+ uart0_ph_pins: uart0-ph-pins {
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pins = "PH0", "PH1";
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function = "uart0";
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};
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};
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+ gic: interrupt-controller@3021000 {
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+ compatible = "arm,gic-400";
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+ reg = <0x03021000 0x1000>,
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+ <0x03022000 0x2000>,
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+ <0x03024000 0x2000>,
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+ <0x03026000 0x2000>;
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+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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+ interrupt-controller;
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+ #interrupt-cells = <3>;
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+ };
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+
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mmc0: mmc@4020000 {
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compatible = "allwinner,sun50i-h6-mmc",
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"allwinner,sun50i-a64-mmc";
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@@ -158,6 +278,8 @@
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resets = <&ccu RST_BUS_MMC0>;
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reset-names = "ahb";
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interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&mmc0_pins>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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@@ -186,6 +308,8 @@
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resets = <&ccu RST_BUS_MMC2>;
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reset-names = "ahb";
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interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&mmc2_pins>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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@@ -235,6 +359,250 @@
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status = "disabled";
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};
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+ emac: ethernet@5020000 {
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+ compatible = "allwinner,sun50i-h6-emac",
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+ "allwinner,sun50i-a64-emac";
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+ syscon = <&syscon>;
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+ reg = <0x05020000 0x10000>;
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+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-names = "macirq";
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+ resets = <&ccu RST_BUS_EMAC>;
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+ reset-names = "stmmaceth";
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+ clocks = <&ccu CLK_BUS_EMAC>;
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+ clock-names = "stmmaceth";
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+ status = "disabled";
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+
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+ mdio: mdio {
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+ compatible = "snps,dwmac-mdio";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ };
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+ };
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+
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+ usb2otg: usb@5100000 {
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+ compatible = "allwinner,sun50i-h6-musb",
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+ "allwinner,sun8i-a33-musb";
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+ reg = <0x05100000 0x0400>;
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+ clocks = <&ccu CLK_BUS_OTG>;
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+ resets = <&ccu RST_BUS_OTG>;
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+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-names = "mc";
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+ phys = <&usb2phy 0>;
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+ phy-names = "usb";
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+ extcon = <&usb2phy 0>;
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+ status = "disabled";
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+ };
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+
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+ usb2phy: phy@5100400 {
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+ compatible = "allwinner,sun50i-h6-usb-phy";
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+ reg = <0x05100400 0x24>,
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+ <0x05101800 0x4>,
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+ <0x05311800 0x4>;
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+ reg-names = "phy_ctrl",
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+ "pmu0",
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+ "pmu3";
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+ clocks = <&ccu CLK_USB_PHY0>,
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+ <&ccu CLK_USB_PHY3>;
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+ clock-names = "usb0_phy",
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+ "usb3_phy";
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+ resets = <&ccu RST_USB_PHY0>,
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+ <&ccu RST_USB_PHY3>;
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+ reset-names = "usb0_reset",
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+ "usb3_reset";
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+ status = "disabled";
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+ #phy-cells = <1>;
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+ };
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+
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+ ehci0: usb@5101000 {
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+ compatible = "allwinner,sun50i-h6-ehci", "generic-ehci";
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+ reg = <0x05101000 0x100>;
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+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&ccu CLK_BUS_OHCI0>,
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+ <&ccu CLK_BUS_EHCI0>,
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+ <&ccu CLK_USB_OHCI0>;
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+ resets = <&ccu RST_BUS_OHCI0>,
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+ <&ccu RST_BUS_EHCI0>;
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+ status = "disabled";
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+ };
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+
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+ ohci0: usb@5101400 {
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+ compatible = "allwinner,sun50i-h6-ohci", "generic-ohci";
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+ reg = <0x05101400 0x100>;
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+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&ccu CLK_BUS_OHCI0>,
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+ <&ccu CLK_USB_OHCI0>;
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+ resets = <&ccu RST_BUS_OHCI0>;
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+ status = "disabled";
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+ };
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+
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+ ehci3: usb@5311000 {
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+ compatible = "allwinner,sun50i-h6-ehci", "generic-ehci";
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+ reg = <0x05311000 0x100>;
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+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&ccu CLK_BUS_OHCI3>,
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+ <&ccu CLK_BUS_EHCI3>,
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+ <&ccu CLK_USB_OHCI3>;
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+ resets = <&ccu RST_BUS_OHCI3>,
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+ <&ccu RST_BUS_EHCI3>;
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+ phys = <&usb2phy 3>;
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+ phy-names = "usb";
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+ status = "disabled";
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+ };
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+
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+ ohci3: usb@5311400 {
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+ compatible = "allwinner,sun50i-h6-ohci", "generic-ohci";
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+ reg = <0x05311400 0x100>;
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+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&ccu CLK_BUS_OHCI3>,
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+ <&ccu CLK_USB_OHCI3>;
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+ resets = <&ccu RST_BUS_OHCI3>;
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+ phys = <&usb2phy 3>;
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+ phy-names = "usb";
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+ status = "disabled";
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+ };
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+
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+ hdmi: hdmi@6000000 {
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+ compatible = "allwinner,sun50i-h6-dw-hdmi";
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+ reg = <0x06000000 0x10000>;
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+ reg-io-width = <1>;
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+ interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>,
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+ <&ccu CLK_HDMI>, <&ccu CLK_HDMI_CEC>,
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+ <&ccu CLK_HDCP>, <&ccu CLK_BUS_HDCP>;
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+ clock-names = "iahb", "isfr", "tmds", "cec", "hdcp",
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+ "hdcp-bus";
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+ resets = <&ccu RST_BUS_HDMI_SUB>, <&ccu RST_BUS_HDCP>;
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+ reset-names = "ctrl", "hdcp";
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+ phys = <&hdmi_phy>;
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+ phy-names = "hdmi-phy";
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&hdmi_pins>;
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+ status = "disabled";
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+
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+ ports {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ hdmi_in: port@0 {
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+ reg = <0>;
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+
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+ hdmi_in_tcon_top: endpoint {
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+ remote-endpoint = <&tcon_top_hdmi_out_hdmi>;
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+ };
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+ };
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+
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+ hdmi_out: port@1 {
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+ reg = <1>;
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+ };
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+ };
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+ };
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+
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+ hdmi_phy: hdmi-phy@6010000 {
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+ compatible = "allwinner,sun50i-h6-hdmi-phy";
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+ reg = <0x06010000 0x10000>;
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+ clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>;
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+ clock-names = "bus", "mod";
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+ resets = <&ccu RST_BUS_HDMI>;
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+ reset-names = "phy";
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+ #phy-cells = <0>;
|
|
|
+ };
|
|
|
+
|
|
|
+ tcon_top: tcon-top@6510000 {
|
|
|
+ compatible = "allwinner,sun50i-h6-tcon-top";
|
|
|
+ reg = <0x06510000 0x1000>;
|
|
|
+ clocks = <&ccu CLK_BUS_TCON_TOP>,
|
|
|
+ <&ccu CLK_TCON_TV0>;
|
|
|
+ clock-names = "bus",
|
|
|
+ "tcon-tv0";
|
|
|
+ clock-output-names = "tcon-top-tv0";
|
|
|
+ resets = <&ccu RST_BUS_TCON_TOP>;
|
|
|
+ reset-names = "rst";
|
|
|
+ #clock-cells = <1>;
|
|
|
+
|
|
|
+ ports {
|
|
|
+ #address-cells = <1>;
|
|
|
+ #size-cells = <0>;
|
|
|
+
|
|
|
+ tcon_top_mixer0_in: port@0 {
|
|
|
+ #address-cells = <1>;
|
|
|
+ #size-cells = <0>;
|
|
|
+ reg = <0>;
|
|
|
+
|
|
|
+ tcon_top_mixer0_in_mixer0: endpoint@0 {
|
|
|
+ reg = <0>;
|
|
|
+ remote-endpoint = <&mixer0_out_tcon_top_mixer0>;
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ tcon_top_mixer0_out: port@1 {
|
|
|
+ #address-cells = <1>;
|
|
|
+ #size-cells = <0>;
|
|
|
+ reg = <1>;
|
|
|
+
|
|
|
+ tcon_top_mixer0_out_tcon_tv: endpoint@2 {
|
|
|
+ reg = <2>;
|
|
|
+ remote-endpoint = <&tcon_tv_in_tcon_top_mixer0>;
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ tcon_top_hdmi_in: port@4 {
|
|
|
+ #address-cells = <1>;
|
|
|
+ #size-cells = <0>;
|
|
|
+ reg = <4>;
|
|
|
+
|
|
|
+ tcon_top_hdmi_in_tcon_tv: endpoint@0 {
|
|
|
+ reg = <0>;
|
|
|
+ remote-endpoint = <&tcon_tv_out_tcon_top>;
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ tcon_top_hdmi_out: port@5 {
|
|
|
+ reg = <5>;
|
|
|
+
|
|
|
+ tcon_top_hdmi_out_hdmi: endpoint {
|
|
|
+ remote-endpoint = <&hdmi_in_tcon_top>;
|
|
|
+ };
|
|
|
+ };
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ tcon_tv: lcd-controller@6515000 {
|
|
|
+ compatible = "allwinner,sun50i-h6-tcon-tv",
|
|
|
+ "allwinner,sun8i-r40-tcon-tv";
|
|
|
+ reg = <0x06515000 0x1000>;
|
|
|
+ interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ clocks = <&ccu CLK_BUS_TCON_TV0>,
|
|
|
+ <&tcon_top CLK_TCON_TOP_TV0>;
|
|
|
+ clock-names = "ahb",
|
|
|
+ "tcon-ch1";
|
|
|
+ resets = <&ccu RST_BUS_TCON_TV0>;
|
|
|
+ reset-names = "lcd";
|
|
|
+
|
|
|
+ ports {
|
|
|
+ #address-cells = <1>;
|
|
|
+ #size-cells = <0>;
|
|
|
+
|
|
|
+ tcon_tv_in: port@0 {
|
|
|
+ reg = <0>;
|
|
|
+
|
|
|
+ tcon_tv_in_tcon_top_mixer0: endpoint {
|
|
|
+ remote-endpoint = <&tcon_top_mixer0_out_tcon_tv>;
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ tcon_tv_out: port@1 {
|
|
|
+ #address-cells = <1>;
|
|
|
+ #size-cells = <0>;
|
|
|
+ reg = <1>;
|
|
|
+
|
|
|
+ tcon_tv_out_tcon_top: endpoint@1 {
|
|
|
+ reg = <1>;
|
|
|
+ remote-endpoint = <&tcon_top_hdmi_in_tcon_tv>;
|
|
|
+ };
|
|
|
+ };
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
r_ccu: clock@7010000 {
|
|
|
compatible = "allwinner,sun50i-h6-r-ccu";
|
|
|
reg = <0x07010000 0x400>;
|
|
@@ -266,7 +634,7 @@
|
|
|
interrupt-controller;
|
|
|
#interrupt-cells = <3>;
|
|
|
|
|
|
- r_i2c_pins: r-i2c {
|
|
|
+ r_i2c_pins: r-i2c-pins {
|
|
|
pins = "PL0", "PL1";
|
|
|
function = "s_i2c";
|
|
|
};
|