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@@ -247,6 +247,7 @@ static int virtex2_slave_post(xilinx_virtex2_slave_selectmap_fns *fn,
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int cookie)
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{
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int ret_val = FPGA_SUCCESS;
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+ int num_done = 0;
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unsigned long ts;
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/*
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@@ -264,12 +265,18 @@ static int virtex2_slave_post(xilinx_virtex2_slave_selectmap_fns *fn,
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/*
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* Check for successful configuration. FPGA INIT_B and DONE
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- * should both be high upon successful configuration.
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+ * should both be high upon successful configuration. Continue pulsing
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+ * clock with data set to all ones until DONE is asserted and for 8
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+ * clock cycles afterwards.
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*/
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ts = get_timer(0);
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- ret_val = FPGA_SUCCESS;
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- while (((*fn->done)(cookie) == FPGA_FAIL) ||
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- (*fn->init)(cookie)) {
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+ while (true) {
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+ if ((*fn->done)(cookie) == FPGA_SUCCESS &&
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+ !((*fn->init)(cookie))) {
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+ if (num_done++ >= 8)
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+ break;
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+ }
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+
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if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT_CONFIG) {
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printf("%s:%d: ** Timeout after %d ticks waiting for DONE to assert and INIT to deassert\n",
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__func__, __LINE__, CONFIG_SYS_FPGA_WAIT_CONFIG);
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@@ -277,6 +284,11 @@ static int virtex2_slave_post(xilinx_virtex2_slave_selectmap_fns *fn,
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ret_val = FPGA_FAIL;
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break;
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}
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+ (*fn->wdata) (0xff, true, cookie);
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+ CONFIG_FPGA_DELAY();
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+ (*fn->clk) (false, true, cookie);
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+ CONFIG_FPGA_DELAY();
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+ (*fn->clk) (true, true, cookie);
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}
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if (ret_val == FPGA_SUCCESS) {
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