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-* Texas Instruments - dp83867 Giga bit ethernet phy
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-
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-Required properties:
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- - reg - The ID number for the phy, usually a small integer
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- - ti,rx-internal-delay - RGMII Recieve Clock Delay - see dt-bindings/net/ti-dp83867.h
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- for applicable values
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- - ti,tx-internal-delay - RGMII Transmit Clock Delay - see dt-bindings/net/ti-dp83867.h
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- for applicable values
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- - ti,fifo-depth - Transmitt FIFO depth- see dt-bindings/net/ti-dp83867.h
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- for applicable values
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- - enet-phy-lane-swap - Indicates that PHY will swap the TX/RX lanes to
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- compensate for the board being designed with the lanes swapped.
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- - enet-phy-no-lane-swap - Indicates that PHY will disable swap of the
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- TX/RX lanes.
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- - ti,clk-output-sel - Muxing option for CLK_OUT pin. See dt-bindings/net/ti-dp83867.h
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- for applicable values. The CLK_OUT pin can also
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- be disabled by this property. When omitted, the
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- PHY's default will be left as is.
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-
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-Default child nodes are standard Ethernet PHY device
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-nodes as described in doc/devicetree/bindings/net/ethernet.txt
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-
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-Example:
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-
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- ethernet-phy@0 {
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- reg = <0>;
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- ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
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- ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
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- ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
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- enet-phy-lane-no-swap;
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- ti,clk-output-sel = <DP83867_CLK_O_SEL_CHN_A_TCLK>;
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- };
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-
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-Datasheet can be found:
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-http://www.ti.com/product/DP83867IR/datasheet
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