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@@ -521,6 +521,20 @@ static const struct mtk_gate_regs sgmii_cg_regs = {
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.flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \
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}
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+static const struct mtk_gate_regs ssusb_cg_regs = {
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+ .set_ofs = 0x30,
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+ .clr_ofs = 0x30,
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+ .sta_ofs = 0x30,
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+};
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+
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+#define GATE_SSUSB(_id, _parent, _shift) { \
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+ .id = _id, \
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+ .parent = _parent, \
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+ .regs = &ssusb_cg_regs, \
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+ .shift = _shift, \
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+ .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \
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+}
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+
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static const struct mtk_gate sgmii_cgs[] = {
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GATE_SGMII(CLK_SGMII_TX250M_EN, CLK_TOP_SSUSB_TX250M, 2),
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GATE_SGMII(CLK_SGMII_RX250M_EN, CLK_TOP_SSUSB_EQ_RX250M, 3),
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@@ -528,6 +542,15 @@ static const struct mtk_gate sgmii_cgs[] = {
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GATE_SGMII(CLK_SGMII_CDR_FB, CLK_TOP_SSUSB_CDR_FB, 5),
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};
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+static const struct mtk_gate ssusb_cgs[] = {
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+ GATE_SSUSB(CLK_SSUSB_U2_PHY_1P_EN, CLK_TOP_TO_U2_PHY_1P, 0),
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+ GATE_SSUSB(CLK_SSUSB_U2_PHY_EN, CLK_TOP_TO_U2_PHY, 1),
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+ GATE_SSUSB(CLK_SSUSB_REF_EN, CLK_TOP_TO_USB3_REF, 5),
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+ GATE_SSUSB(CLK_SSUSB_SYS_EN, CLK_TOP_TO_USB3_SYS, 6),
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+ GATE_SSUSB(CLK_SSUSB_MCU_EN, CLK_TOP_AXI_SEL, 7),
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+ GATE_SSUSB(CLK_SSUSB_DMA_EN, CLK_TOP_HIF_SEL, 8),
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+};
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+
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static const struct mtk_clk_tree mt7622_clk_tree = {
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.xtal_rate = 25 * MHZ,
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.xtal2_rate = 25 * MHZ,
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@@ -630,6 +653,11 @@ static int mt7622_sgmiisys_probe(struct udevice *dev)
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return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, sgmii_cgs);
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}
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+static int mt7622_ssusbsys_probe(struct udevice *dev)
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+{
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+ return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, ssusb_cgs);
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+}
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+
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static const struct udevice_id mt7622_apmixed_compat[] = {
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{ .compatible = "mediatek,mt7622-apmixedsys" },
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{ }
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@@ -670,6 +698,11 @@ static const struct udevice_id mt7622_mcucfg_compat[] = {
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{ }
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};
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+static const struct udevice_id mt7622_ssusbsys_compat[] = {
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+ { .compatible = "mediatek,mt7622-ssusbsys" },
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+ { }
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+};
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+
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U_BOOT_DRIVER(mtk_mcucfg) = {
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.name = "mt7622-mcucfg",
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.id = UCLASS_SYSCON,
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@@ -746,3 +779,12 @@ U_BOOT_DRIVER(mtk_clk_sgmiisys) = {
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.priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
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.ops = &mtk_clk_gate_ops,
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};
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+
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+U_BOOT_DRIVER(mtk_clk_ssusbsys) = {
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+ .name = "mt7622-clock-ssusbsys",
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+ .id = UCLASS_CLK,
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+ .of_match = mt7622_ssusbsys_compat,
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+ .probe = mt7622_ssusbsys_probe,
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+ .priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
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+ .ops = &mtk_clk_gate_ops,
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+};
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