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@@ -36,6 +36,54 @@
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DECLARE_GLOBAL_DATA_PTR;
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+#ifdef CONFIG_SYS_FSL_ERRATUM_A006261
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+void fsl_erratum_a006261_workaround(struct ccsr_usb_phy __iomem *usb_phy)
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+{
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+#ifdef CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
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+ u32 xcvrprg = in_be32(&usb_phy->port1.xcvrprg);
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+
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+ /* Increase Disconnect Threshold by 50mV */
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+ xcvrprg &= ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK |
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+ INC_DCNT_THRESHOLD_50MV;
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+ /* Enable programming of USB High speed Disconnect threshold */
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+ xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN;
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+ out_be32(&usb_phy->port1.xcvrprg, xcvrprg);
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+
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+ xcvrprg = in_be32(&usb_phy->port2.xcvrprg);
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+ /* Increase Disconnect Threshold by 50mV */
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+ xcvrprg &= ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK |
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+ INC_DCNT_THRESHOLD_50MV;
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+ /* Enable programming of USB High speed Disconnect threshold */
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+ xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN;
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+ out_be32(&usb_phy->port2.xcvrprg, xcvrprg);
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+#else
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+
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+ u32 temp = 0;
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+ u32 status = in_be32(&usb_phy->status1);
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+
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+ u32 squelch_prog_rd_0_2 =
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+ (status >> CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_0)
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+ & CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK;
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+
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+ u32 squelch_prog_rd_3_5 =
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+ (status >> CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_3)
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+ & CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK;
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+
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+ setbits_be32(&usb_phy->config1,
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+ CONFIG_SYS_FSL_USB_HS_DISCNCT_INC);
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+ setbits_be32(&usb_phy->config2,
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+ CONFIG_SYS_FSL_USB_RX_AUTO_CAL_RD_WR_SEL);
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+
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+ temp = squelch_prog_rd_0_2 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_0;
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+ out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp);
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+
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+ temp = squelch_prog_rd_3_5 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_3;
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+ out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp);
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+#endif
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+}
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+#endif
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+
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+
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#ifdef CONFIG_QE
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extern qe_iop_conf_t qe_iop_conf_tab[];
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extern void qe_config_iopin(u8 port, u8 pin, int dir,
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@@ -625,6 +673,10 @@ skip_l2:
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{
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struct ccsr_usb_phy __iomem *usb_phy1 =
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(void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
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+#ifdef CONFIG_SYS_FSL_ERRATUM_A006261
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+ if (has_erratum_a006261())
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+ fsl_erratum_a006261_workaround(usb_phy1);
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+#endif
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out_be32(&usb_phy1->usb_enable_override,
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CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
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}
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@@ -633,6 +685,10 @@ skip_l2:
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{
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struct ccsr_usb_phy __iomem *usb_phy2 =
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(void *)CONFIG_SYS_MPC85xx_USB2_PHY_ADDR;
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+#ifdef CONFIG_SYS_FSL_ERRATUM_A006261
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+ if (has_erratum_a006261())
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+ fsl_erratum_a006261_workaround(usb_phy2);
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+#endif
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out_be32(&usb_phy2->usb_enable_override,
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CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
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}
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@@ -672,8 +728,14 @@ skip_l2:
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CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN);
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setbits_be32(&usb_phy->port2.pwrfltcfg,
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CONFIG_SYS_FSL_USB_PWRFLT_CR_EN);
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+
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+#ifdef CONFIG_SYS_FSL_ERRATUM_A006261
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+ if (has_erratum_a006261())
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+ fsl_erratum_a006261_workaround(usb_phy);
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#endif
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+#endif /* CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE */
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+
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#ifdef CONFIG_FMAN_ENET
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fman_enet_init();
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#endif
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