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@@ -14,8 +14,6 @@
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#include <asm/mach-imx/video.h>
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#include <mmc.h>
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#include <fsl_esdhc_imx.h>
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-#include <miiphy.h>
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-#include <netdev.h>
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#include <asm/arch/mxc_hdmi.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/io.h>
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@@ -26,9 +24,6 @@ DECLARE_GLOBAL_DATA_PTR;
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PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
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PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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-#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
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- PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
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-
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static iomux_v3_cfg_t const uart1_pads[] = {
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MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
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@@ -39,43 +34,12 @@ static iomux_v3_cfg_t const uart2_pads[] = {
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MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
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};
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-static iomux_v3_cfg_t const enet_pads[] = {
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- MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
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- MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
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- MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
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- MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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- MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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- MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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- MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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- MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
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- MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
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- MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
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- MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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- MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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- MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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- MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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- MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
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- /* AR8035 PHY Reset */
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- MX6_PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL),
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-};
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-
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int dram_init(void)
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{
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gd->ram_size = 2048ul * 1024 * 1024;
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return 0;
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}
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-static void setup_iomux_enet(void)
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-{
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- imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
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-
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- /* Reset AR8035 PHY */
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- gpio_request(IMX_GPIO_NR(1, 25), "ETH_PHY_RESET");
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- gpio_direction_output(IMX_GPIO_NR(1, 25) , 0);
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- udelay(500);
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- gpio_set_value(IMX_GPIO_NR(1, 25), 1);
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-}
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-
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static void setup_iomux_uart(void)
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{
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imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
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@@ -184,45 +148,6 @@ static void setup_display(void)
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}
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#endif /* CONFIG_VIDEO_IPUV3 */
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-static int ar8035_phy_fixup(struct phy_device *phydev)
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-{
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- unsigned short val;
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-
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- /* To enable AR8035 ouput a 125MHz clk from CLK_25M */
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- phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
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- phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
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- phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
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-
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- val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
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- val &= 0xffe3;
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- val |= 0x18;
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- phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
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-
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- /* introduce tx clock delay */
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- phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
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- val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
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- val |= 0x0100;
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- phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
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-
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- return 0;
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-}
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-
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-int board_phy_config(struct phy_device *phydev)
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-{
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- ar8035_phy_fixup(phydev);
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-
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- if (phydev->drv->config)
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- phydev->drv->config(phydev);
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-
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- return 0;
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-}
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-
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-int board_eth_init(bd_t *bis)
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-{
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- setup_iomux_enet();
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- return cpu_eth_init(bis);
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-}
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-
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int board_early_init_f(void)
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{
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setup_iomux_uart();
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