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+/* SPDX-License-Identifier: GPL-2.0+ */
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+/*
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+ * Adapted from Linux kernel driver
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+ * Copyright (C) 2017 Texas Instruments
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+ * Author: Kishon Vijay Abraham I <kishon@ti.com>
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+ *
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+ * (C) Copyright 2019
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+ * Ramon Fried <ramon.fried@gmail.com>
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+ */
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+
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+#ifndef _PCI_EP_H
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+#define _PCI_EP_H
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+
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+#include <pci.h>
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+
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+/**
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+ * enum pci_interrupt_pin - PCI INTx interrupt values
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+ * @PCI_INTERRUPT_UNKNOWN: Unknown or unassigned interrupt
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+ * @PCI_INTERRUPT_INTA: PCI INTA pin
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+ * @PCI_INTERRUPT_INTB: PCI INTB pin
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+ * @PCI_INTERRUPT_INTC: PCI INTC pin
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+ * @PCI_INTERRUPT_INTD: PCI INTD pin
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+ *
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+ * Corresponds to values for legacy PCI INTx interrupts, as can be found in the
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+ * PCI_INTERRUPT_PIN register.
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+ */
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+enum pci_interrupt_pin {
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+ PCI_INTERRUPT_UNKNOWN,
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+ PCI_INTERRUPT_INTA,
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+ PCI_INTERRUPT_INTB,
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+ PCI_INTERRUPT_INTC,
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+ PCI_INTERRUPT_INTD,
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+};
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+
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+enum pci_barno {
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+ BAR_0,
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+ BAR_1,
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+ BAR_2,
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+ BAR_3,
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+ BAR_4,
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+ BAR_5,
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+};
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+
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+enum pci_ep_irq_type {
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+ PCI_EP_IRQ_UNKNOWN,
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+ PCI_EP_IRQ_LEGACY,
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+ PCI_EP_IRQ_MSI,
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+ PCI_EP_IRQ_MSIX,
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+};
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+
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+/**
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+ * struct pci_bar - represents the BAR (Base Address Register) of EP device
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+ * @phys_addr: physical address that should be mapped to the BAR
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+ * @size: the size of the address space present in BAR
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+ * pci_barno: number of pci BAR to set (0..5)
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+ * @flags: BAR access flags
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+ */
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+struct pci_bar {
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+ dma_addr_t phys_addr;
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+ size_t size;
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+ enum pci_barno barno;
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+ int flags;
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+};
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+
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+/**
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+ * struct pci_ep_header - represents standard configuration header
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+ * @vendorid: identifies device manufacturer
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+ * @deviceid: identifies a particular device
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+ * @revid: specifies a device-specific revision identifier
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+ * @progif_code: identifies a specific register-level programming interface
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+ * @subclass_code: identifies more specifically the function of the device
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+ * @baseclass_code: broadly classifies the type of function the device performs
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+ * @cache_line_size: specifies the system cacheline size in units of DWORDs
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+ * @subsys_vendor_id: vendor of the add-in card or subsystem
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+ * @subsys_id: id specific to vendor
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+ * @interrupt_pin: interrupt pin the device (or device function) uses
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+ */
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+struct pci_ep_header {
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+ u16 vendorid;
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+ u16 deviceid;
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+ u8 revid;
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+ u8 progif_code;
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+ u8 subclass_code;
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+ u8 baseclass_code;
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+ u8 cache_line_size;
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+ u16 subsys_vendor_id;
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+ u16 subsys_id;
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+ enum pci_interrupt_pin interrupt_pin;
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+};
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+
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+/* PCI endpoint operations */
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+struct pci_ep_ops {
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+ /**
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+ * write_header() - Write a PCI configuration space header
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+ *
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+ * @dev: device to write to
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+ * @func_num: EP function to fill
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+ * @hdr: header to write
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+ * @return 0 if OK, -ve on error
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+ */
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+ int (*write_header)(struct udevice *dev, uint func_num,
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+ struct pci_ep_header *hdr);
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+ /**
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+ * read_header() - Read a PCI configuration space header
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+ *
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+ * @dev: device to write to
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+ * @func_num: EP function to fill
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+ * @hdr: header to read to
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+ * @return 0 if OK, -ve on error
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+ */
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+ int (*read_header)(struct udevice *dev, uint func_num,
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+ struct pci_ep_header *hdr);
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+ /**
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+ * set_bar() - Set BAR (Base Address Register) properties
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+ *
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+ * @dev: device to set
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+ * @func_num: EP function to set
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+ * @bar: bar data
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+ * @return 0 if OK, -ve on error
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+ */
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+ int (*set_bar)(struct udevice *dev, uint func_num,
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+ struct pci_bar *bar);
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+ /**
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+ * read_bar() - Read BAR (Base Address Register) properties
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+ *
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+ * @dev: device to read
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+ * @func_num: EP function to read
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+ * @bar: struct to copy data to
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+ * @barno: bar number to read
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+ * @return 0 if OK, -ve on error
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+ */
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+ int (*read_bar)(struct udevice *dev, uint func_num,
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+ struct pci_bar *bar, enum pci_barno barno);
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+ /**
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+ * clear_bar() - clear BAR (Base Address Register)
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+ *
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+ * @dev: device to clear
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+ * @func_num: EP function to clear
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+ * @bar: bar number
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+ * @return 0 if OK, -ve on error
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+ */
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+ int (*clear_bar)(struct udevice *dev, uint func_num,
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+ enum pci_barno bar);
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+ /**
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+ * map_addr() - map CPU address to PCI address
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+ *
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+ * outband region is used in order to generate PCI read/write
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+ * transaction from local memory/write.
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+ *
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+ * @dev: device to set
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+ * @func_num: EP function to set
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+ * @addr: local physical address base
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+ * @pci_addr: pci address to translate to
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+ * @size: region size
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+ * @return 0 if OK, -ve on error
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+ */
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+ int (*map_addr)(struct udevice *dev, uint func_num,
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+ phys_addr_t addr, u64 pci_addr, size_t size);
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+ /**
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+ * unmap_addr() - unmap CPU address to PCI address
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+ *
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+ * unmap previously mapped region.
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+ *
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+ * @dev: device to set
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+ * @func_num: EP function to set
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+ * @addr: local physical address base
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+ * @return 0 if OK, -ve on error
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+ */
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+ int (*unmap_addr)(struct udevice *dev, uint func_num,
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+ phys_addr_t addr);
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+ /**
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+ * set_msi() - set msi capability property
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+ *
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+ * set the number of required MSI vectors the device
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+ * needs for operation.
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+ *
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+ * @dev: device to set
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+ * @func_num: EP function to set
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+ * @interrupts: required interrupts count
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+ * @return 0 if OK, -ve on error
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+ */
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+ int (*set_msi)(struct udevice *dev, uint func_num, uint interrupts);
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+
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+ /**
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+ * get_msi() - get the number of MSI interrupts allocated by the host.
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+ *
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+ * Read the Multiple Message Enable bitfield from
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+ * Message control register.
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+ *
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+ * @dev: device to use
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+ * @func_num: EP function to use
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+ * @return msi count if OK, -EINVAL if msi were not enabled at host.
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+ */
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+ int (*get_msi)(struct udevice *dev, uint func_num);
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+
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+ /**
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+ * set_msix() - set msix capability property
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+ *
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+ * set the number of required MSIx vectors the device
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+ * needs for operation.
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+ *
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+ * @dev: device to set
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+ * @func_num: EP function to set
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+ * @interrupts: required interrupts count
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+ * @return 0 if OK, -ve on error
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+ */
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+ int (*set_msix)(struct udevice *dev, uint func_num,
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+ uint interrupts);
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+
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+ /**
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+ * get_msix() - get the number of MSIx interrupts allocated by the host.
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+ *
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+ * Read the Multiple Message Enable bitfield from
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+ * Message control register.
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+ *
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+ * @dev: device to use
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+ * @func_num: EP function to use
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+ * @return msi count if OK, -EINVAL if msi were not enabled at host.
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+ */
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+ int (*get_msix)(struct udevice *dev, uint func_num);
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+
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+ /**
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+ * raise_irq() - raise a legacy, MSI or MSI-X interrupt
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+ *
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+ * @dev: device to set
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+ * @func_num: EP function to set
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+ * @type: type of irq to send
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+ * @interrupt_num: interrupt vector to use
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+ * @return 0 if OK, -ve on error
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+ */
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+ int (*raise_irq)(struct udevice *dev, uint func_num,
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+ enum pci_ep_irq_type type, uint interrupt_num);
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+ /**
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+ * start() - start the PCI link
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+ *
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+ * @dev: device to set
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+ * @return 0 if OK, -ve on error
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+ */
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+ int (*start)(struct udevice *dev);
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+
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+ /**
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+ * stop() - stop the PCI link
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+ *
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+ * @dev: device to set
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+ * @return 0 if OK, -ve on error
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+ */
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+ int (*stop)(struct udevice *dev);
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+};
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+
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+#define pci_ep_get_ops(dev) ((struct pci_ep_ops *)(dev)->driver->ops)
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+
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+/**
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+ * pci_ep_write_header() - Write a PCI configuration space header
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+ *
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+ * @dev: device to write to
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+ * @func_num: EP function to fill
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+ * @hdr: header to write
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+ * @return 0 if OK, -ve on error
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+ */
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+int pci_ep_write_header(struct udevice *dev, uint func_num,
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+ struct pci_ep_header *hdr);
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+
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+/**
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+ * dm_pci_ep_read_header() - Read a PCI configuration space header
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+ *
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+ * @dev: device to write to
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+ * @func_num: EP function to fill
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+ * @hdr: header to read to
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+ * @return 0 if OK, -ve on error
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+ */
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+int pci_ep_read_header(struct udevice *dev, uint func_num,
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+ struct pci_ep_header *hdr);
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+/**
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+ * pci_ep_set_bar() - Set BAR (Base Address Register) properties
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+ *
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+ * @dev: device to set
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+ * @func_num: EP function to set
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+ * @bar: bar data
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+ * @return 0 if OK, -ve on error
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+ */
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+int pci_ep_set_bar(struct udevice *dev, uint func_num, struct pci_bar *bar);
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+
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+/**
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+ * pci_ep_read_bar() - Read BAR (Base Address Register) properties
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+ *
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+ * @dev: device to read
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+ * @func_num: EP function to read
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+ * @bar: struct to copy data to
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+ * @barno: bar number to read
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+ * @return 0 if OK, -ve on error
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+ */
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+int pci_ep_read_bar(struct udevice *dev, uint func_no, struct pci_bar *ep_bar,
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+ enum pci_barno barno);
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+
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+/**
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+ * pci_ep_clear_bar() - Clear BAR (Base Address Register)
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+ * mark the BAR as empty so host won't map it.
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+ * @dev: device to clear
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+ * @func_num: EP function to clear
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+ * @bar: bar number
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+ * @return 0 if OK, -ve on error
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+ */
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+int pci_ep_clear_bar(struct udevice *dev, uint func_num, enum pci_barno bar);
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+/**
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+ * pci_ep_map_addr() - map CPU address to PCI address
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+ *
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+ * outband region is used in order to generate PCI read/write
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+ * transaction from local memory/write.
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+ *
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+ * @dev: device to set
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+ * @func_num: EP function to set
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+ * @addr: local physical address base
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+ * @pci_addr: pci address to translate to
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+ * @size: region size
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+ * @return 0 if OK, -ve on error
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+ */
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+int pci_ep_map_addr(struct udevice *dev, uint func_num, phys_addr_t addr,
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+ u64 pci_addr, size_t size);
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+/**
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+ * pci_ep_unmap_addr() - unmap CPU address to PCI address
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+ *
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+ * unmap previously mapped region.
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+ *
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+ * @dev: device to set
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+ * @func_num: EP function to set
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+ * @addr: local physical address base
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+ * @return 0 if OK, -ve on error
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+ */
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+int pci_ep_unmap_addr(struct udevice *dev, uint func_num, phys_addr_t addr);
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+
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+/**
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+ * pci_ep_set_msi() - set msi capability property
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+ *
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+ * set the number of required MSI vectors the device
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+ * needs for operation.
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+ *
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+ * @dev: device to set
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+ * @func_num: EP function to set
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+ * @interrupts: required interrupts count
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+ * @return 0 if OK, -ve on error
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+ */
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+int pci_ep_set_msi(struct udevice *dev, uint func_num, uint interrupts);
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+
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+/**
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+ * pci_ep_get_msi() - get the number of MSI interrupts allocated by the host.
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+ *
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+ * Read the Multiple Message Enable bitfield from
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+ * Message control register.
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+ *
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+ * @dev: device to use
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+ * @func_num: EP function to use
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+ * @return msi count if OK, -EINVAL if msi were not enabled at host.
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+ */
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+int pci_ep_get_msi(struct udevice *dev, uint func_num);
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+
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+/**
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+ * pci_ep_set_msix() - set msi capability property
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+ *
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+ * set the number of required MSIx vectors the device
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+ * needs for operation.
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+ *
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+ * @dev: device to set
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+ * @func_num: EP function to set
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+ * @interrupts: required interrupts count
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+ * @return 0 if OK, -ve on error
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+ */
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+int pci_ep_set_msix(struct udevice *dev, uint func_num, uint interrupts);
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+
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+/**
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+ * pci_ep_get_msix() - get the number of MSIx interrupts allocated by the host.
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+ *
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+ * Read the Multiple Message Enable bitfield from
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+ * Message control register.
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+ *
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+ * @dev: device to use
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+ * @func_num: EP function to use
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+ * @return msi count if OK, -EINVAL if msi were not enabled at host.
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+ */
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+int pci_ep_get_msix(struct udevice *dev, uint func_num);
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+
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+/**
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+ * pci_ep_raise_irq() - raise a legacy, MSI or MSI-X interrupt
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+ *
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+ * @dev: device to set
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+ * @func_num: EP function to set
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+ * @type: type of irq to send
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+ * @interrupt_num: interrupt vector to use
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+ * @return 0 if OK, -ve on error
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+ */
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+int pci_ep_raise_irq(struct udevice *dev, uint func_num,
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+ enum pci_ep_irq_type type, uint interrupt_num);
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+/**
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+ * pci_ep_start() - start the PCI link
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+ *
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+ * Enable PCI endpoint device and start link
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+ * process.
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+ *
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+ * @dev: device to set
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+ * @return 0 if OK, -ve on error
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+ */
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+int pci_ep_start(struct udevice *dev);
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+
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+/**
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+ * pci_ep_stop() - stop the PCI link
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+ *
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+ * Disable PCI endpoint device and stop
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+ * link.
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+ *
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+ * @dev: device to set
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+ * @return 0 if OK, -ve on error
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+ */
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+int pci_ep_stop(struct udevice *dev);
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+
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+#endif
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