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@@ -12,6 +12,9 @@ describes the fields added for clock tree initialization which are not present
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in Linux binding for compatible "st,stm32mp1-rcc" defined in st,stm32mp1-rcc.txt
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file.
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+This parent node may optionally have additional children nodes which define
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+specific init values for RCC elements.
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+
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The added properties for clock tree initialization are:
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Required properties:
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@@ -78,13 +81,16 @@ Required properties:
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>;
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Optional Properties:
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-- st,pll : A specific PLL configuration, including frequency.
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+- children for a PLL configuration with "st,stm32mp1-pll" compatible
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- PLL children nodes for PLL1 to PLL4 (see ref manual for details)
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- are listed with associated index 0 to 3 (st,pll@0 to st,pll@3).
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- PLLx is off when the associated node is absent.
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+ each PLL children nodes for PLL1 to PLL4 (see ref manual for details)
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+ are listed with associated reg 0 to 3.
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+ PLLx is off when the associated node is absent or deactivated.
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Here are the available properties for each PLL node:
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+ - compatible: should be "st,stm32mp1-pll"
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+
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+ - reg: index of the pll instance
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- cfg: The parameters for PLL configuration in the following order:
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DIVM DIVN DIVP DIVQ DIVR Output.
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@@ -118,18 +124,26 @@ Optional Properties:
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Example:
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st,pll@0 {
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+ compatible = "st,stm32mp1-pll";
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+ reg = <0>;
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cfg = < 1 53 0 0 0 1 >;
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frac = < 0x810 >;
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};
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st,pll@1 {
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+ compatible = "st,stm32mp1-pll";
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+ reg = <1>;
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cfg = < 1 43 1 0 0 PQR(0,1,1) >;
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csg = < 10 20 1 >;
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};
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st,pll@2 {
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+ compatible = "st,stm32mp1-pll";
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+ reg = <2>;
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cfg = < 2 85 3 13 3 0 >;
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csg = < 10 20 SSCG_MODE_CENTER_SPREAD >;
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};
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st,pll@3 {
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+ compatible = "st,stm32mp1-pll";
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+ reg = <3>;
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cfg = < 2 78 4 7 9 3 >;
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};
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@@ -277,6 +291,8 @@ Example of clock tree initialization
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u-boot,dm-pre-reloc;
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compatible = "st,stm32mp1-rcc", "syscon";
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reg = <0x50000000 0x1000>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
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@@ -347,6 +363,8 @@ Example of clock tree initialization
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/* VCO = 1300.0 MHz => P = 650 (CPU) */
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pll1: st,pll@0 {
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+ compatible = "st,stm32mp1-pll";
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+ reg = <0>;
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cfg = < 2 80 0 0 0 PQR(1,0,0) >;
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frac = < 0x800 >;
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u-boot,dm-pre-reloc;
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@@ -355,6 +373,8 @@ Example of clock tree initialization
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/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU),
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R = 533 (DDR) */
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pll2: st,pll@1 {
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+ compatible = "st,stm32mp1-pll";
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+ reg = <1>;
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cfg = < 2 65 1 0 0 PQR(1,1,1) >;
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frac = < 0x1400 >;
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u-boot,dm-pre-reloc;
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@@ -362,6 +382,8 @@ Example of clock tree initialization
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/* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
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pll3: st,pll@2 {
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+ compatible = "st,stm32mp1-pll";
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+ reg = <2>;
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cfg = < 1 33 1 16 36 PQR(1,1,1) >;
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frac = < 0x1a04 >;
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u-boot,dm-pre-reloc;
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@@ -369,6 +391,8 @@ Example of clock tree initialization
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/* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
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pll4: st,pll@3 {
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+ compatible = "st,stm32mp1-pll";
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+ reg = <3>;
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cfg = < 3 98 5 7 7 PQR(1,1,1) >;
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u-boot,dm-pre-reloc;
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};
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