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@@ -20,6 +20,7 @@
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#define UBOOT_DM_CLK_IMX_PLLV3_SYS "imx_clk_pllv3_sys"
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#define UBOOT_DM_CLK_IMX_PLLV3_USB "imx_clk_pllv3_usb"
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#define UBOOT_DM_CLK_IMX_PLLV3_AV "imx_clk_pllv3_av"
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+#define UBOOT_DM_CLK_IMX_PLLV3_ENET "imx_clk_pllv3_enet"
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#define PLL_NUM_OFFSET 0x10
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#define PLL_DENOM_OFFSET 0x20
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@@ -36,6 +37,7 @@ struct clk_pllv3 {
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u32 enable_bit;
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u32 div_mask;
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u32 div_shift;
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+ unsigned long ref_clock;
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};
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#define to_clk_pllv3(_clk) container_of(_clk, struct clk_pllv3, clk)
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@@ -232,6 +234,19 @@ static const struct clk_ops clk_pllv3_av_ops = {
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.set_rate = clk_pllv3_av_set_rate,
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};
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+static ulong clk_pllv3_enet_get_rate(struct clk *clk)
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+{
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+ struct clk_pllv3 *pll = to_clk_pllv3(clk);
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+
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+ return pll->ref_clock;
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+}
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+
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+static const struct clk_ops clk_pllv3_enet_ops = {
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+ .enable = clk_pllv3_generic_enable,
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+ .disable = clk_pllv3_generic_disable,
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+ .get_rate = clk_pllv3_enet_get_rate,
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+};
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+
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struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
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const char *parent_name, void __iomem *base,
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u32 div_mask)
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@@ -269,6 +284,10 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
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pll->div_shift = 0;
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pll->powerup_set = false;
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break;
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+ case IMX_PLLV3_ENET:
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+ drv_name = UBOOT_DM_CLK_IMX_PLLV3_ENET;
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+ pll->ref_clock = 500000000;
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+ break;
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default:
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kfree(pll);
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return ERR_PTR(-ENOTSUPP);
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@@ -314,3 +333,9 @@ U_BOOT_DRIVER(clk_pllv3_av) = {
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.ops = &clk_pllv3_av_ops,
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.flags = DM_FLAG_PRE_RELOC,
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};
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+
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+U_BOOT_DRIVER(clk_pllv3_enet) = {
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+ .name = UBOOT_DM_CLK_IMX_PLLV3_ENET,
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+ .id = UCLASS_CLK,
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+ .ops = &clk_pllv3_enet_ops,
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+};
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