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@@ -0,0 +1,135 @@
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+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
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+/*
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+ * Copyright (C) 2019, STMicroelectronics - All Rights Reserved
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+ */
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+
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+#include <common.h>
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+#include <clk.h>
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+#include <dm.h>
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+#include <syscon.h>
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+#include <wdt.h>
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+#include <asm/io.h>
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+#include <linux/iopoll.h>
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+
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+/* IWDG registers */
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+#define IWDG_KR 0x00 /* Key register */
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+#define IWDG_PR 0x04 /* Prescaler Register */
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+#define IWDG_RLR 0x08 /* ReLoad Register */
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+#define IWDG_SR 0x0C /* Status Register */
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+
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+/* IWDG_KR register bit mask */
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+#define KR_KEY_RELOAD 0xAAAA /* Reload counter enable */
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+#define KR_KEY_ENABLE 0xCCCC /* Peripheral enable */
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+#define KR_KEY_EWA 0x5555 /* Write access enable */
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+
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+/* IWDG_PR register bit values */
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+#define PR_256 0x06 /* Prescaler set to 256 */
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+
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+/* IWDG_RLR register values */
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+#define RLR_MAX 0xFFF /* Max value supported by reload register */
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+
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+/* IWDG_SR register bit values */
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+#define SR_PVU BIT(0) /* Watchdog prescaler value update */
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+#define SR_RVU BIT(1) /* Watchdog counter reload value update */
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+
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+struct stm32mp_wdt_priv {
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+ fdt_addr_t base; /* registers addr in physical memory */
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+ unsigned long wdt_clk_rate; /* Watchdog dedicated clock rate */
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+};
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+
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+static int stm32mp_wdt_reset(struct udevice *dev)
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+{
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+ struct stm32mp_wdt_priv *priv = dev_get_priv(dev);
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+
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+ writel(KR_KEY_RELOAD, priv->base + IWDG_KR);
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+
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+ return 0;
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+}
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+
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+static int stm32mp_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags)
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+{
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+ struct stm32mp_wdt_priv *priv = dev_get_priv(dev);
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+ int reload;
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+ u32 val;
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+ int ret;
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+
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+ /* Prescaler fixed to 256 */
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+ reload = timeout_ms * priv->wdt_clk_rate / 256;
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+ if (reload > RLR_MAX + 1)
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+ /* Force to max watchdog counter reload value */
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+ reload = RLR_MAX + 1;
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+ else if (!reload)
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+ /* Force to min watchdog counter reload value */
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+ reload = priv->wdt_clk_rate / 256;
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+
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+ /* Set prescaler & reload registers */
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+ writel(KR_KEY_EWA, priv->base + IWDG_KR);
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+ writel(PR_256, priv->base + IWDG_PR);
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+ writel(reload - 1, priv->base + IWDG_RLR);
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+
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+ /* Enable watchdog */
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+ writel(KR_KEY_ENABLE, priv->base + IWDG_KR);
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+
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+ /* Wait for the registers to be updated */
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+ ret = readl_poll_timeout(priv->base + IWDG_SR, val,
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+ val & (SR_PVU | SR_RVU), CONFIG_SYS_HZ);
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+
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+ if (ret < 0) {
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+ pr_err("Updating IWDG registers timeout");
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+ return -ETIMEDOUT;
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+ }
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+
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+ return 0;
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+}
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+
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+static int stm32mp_wdt_probe(struct udevice *dev)
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+{
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+ struct stm32mp_wdt_priv *priv = dev_get_priv(dev);
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+ struct clk clk;
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+ int ret;
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+
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+ debug("IWDG init\n");
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+
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+ priv->base = devfdt_get_addr(dev);
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+ if (priv->base == FDT_ADDR_T_NONE)
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+ return -EINVAL;
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+
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+ /* Enable clock */
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+ ret = clk_get_by_name(dev, "pclk", &clk);
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+ if (ret)
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+ return ret;
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+
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+ ret = clk_enable(&clk);
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+ if (ret)
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+ return ret;
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+
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+ /* Get LSI clock */
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+ ret = clk_get_by_name(dev, "lsi", &clk);
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+ if (ret)
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+ return ret;
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+
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+ priv->wdt_clk_rate = clk_get_rate(&clk);
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+
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+ debug("IWDG init done\n");
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+
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+ return 0;
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+}
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+
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+static const struct wdt_ops stm32mp_wdt_ops = {
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+ .start = stm32mp_wdt_start,
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+ .reset = stm32mp_wdt_reset,
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+};
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+
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+static const struct udevice_id stm32mp_wdt_match[] = {
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+ { .compatible = "st,stm32mp1-iwdg" },
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+ { /* sentinel */ }
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+};
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+
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+U_BOOT_DRIVER(stm32mp_wdt) = {
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+ .name = "stm32mp-wdt",
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+ .id = UCLASS_WDT,
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+ .of_match = stm32mp_wdt_match,
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+ .priv_auto_alloc_size = sizeof(struct stm32mp_wdt_priv),
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+ .probe = stm32mp_wdt_probe,
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+ .ops = &stm32mp_wdt_ops,
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+};
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