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@@ -11,6 +11,8 @@
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#include <clk-uclass.h>
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#include <div64.h>
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#include <dm.h>
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+#include <regmap.h>
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+#include <syscon.h>
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#include <dt-bindings/clock/gxbb-clkc.h>
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#include "clk_meson.h"
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@@ -65,7 +67,7 @@
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#define XTAL_RATE 24000000
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struct meson_clk {
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- void __iomem *addr;
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+ struct regmap *map;
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};
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static ulong meson_div_get_rate(struct clk *clk, unsigned long id);
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@@ -217,8 +219,8 @@ static int meson_set_gate_by_id(struct clk *clk, unsigned long id, bool on)
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debug("%s: really %sabling %ld\n", __func__, on ? "en" : "dis", id);
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- clrsetbits_le32(priv->addr + gate->reg,
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- BIT(gate->bit), on ? BIT(gate->bit) : 0);
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+ regmap_update_bits(priv->map, gate->reg,
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+ BIT(gate->bit), on ? BIT(gate->bit) : 0);
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/* Propagate to next gate(s) */
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switch (id) {
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@@ -269,7 +271,7 @@ static ulong meson_div_get_rate(struct clk *clk, unsigned long id)
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unsigned int rate, parent_rate;
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struct parm *parm;
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int parent;
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- u32 reg;
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+ uint reg;
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switch (id) {
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case CLKID_VPU_0_DIV:
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@@ -292,7 +294,7 @@ static ulong meson_div_get_rate(struct clk *clk, unsigned long id)
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return -ENOENT;
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}
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- reg = readl(priv->addr + parm->reg_off);
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+ regmap_read(priv->map, parm->reg_off, ®);
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reg = PARM_GET(parm->width, parm->shift, reg);
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debug("%s: div of %ld is %d\n", __func__, id, reg + 1);
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@@ -318,7 +320,6 @@ static ulong meson_div_set_rate(struct clk *clk, unsigned long id, ulong rate,
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unsigned long parent_rate;
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struct parm *parm;
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int parent;
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- u32 reg;
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int ret;
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if (current_rate == rate)
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@@ -383,9 +384,8 @@ static ulong meson_div_set_rate(struct clk *clk, unsigned long id, ulong rate,
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debug("%s: setting div of %ld to %d\n", __func__, id, new_div);
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- reg = readl(priv->addr + parm->reg_off);
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- writel(PARM_SET(parm->width, parm->shift, reg, new_div - 1),
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- priv->addr + parm->reg_off);
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+ regmap_update_bits(priv->map, parm->reg_off, SETPMASK(parm->width, parm->shift),
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+ (new_div - 1) << parm->shift);
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debug("%s: new rate of %ld is %ld\n",
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__func__, id, meson_div_get_rate(clk, id));
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@@ -446,7 +446,7 @@ static ulong meson_mux_get_parent(struct clk *clk, unsigned long id)
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struct meson_clk *priv = dev_get_priv(clk->dev);
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struct parm *parm;
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int *parents;
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- u32 reg;
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+ uint reg;
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switch (id) {
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case CLKID_VPU:
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@@ -477,7 +477,7 @@ static ulong meson_mux_get_parent(struct clk *clk, unsigned long id)
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return -ENOENT;
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}
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- reg = readl(priv->addr + parm->reg_off);
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+ regmap_read(priv->map, parm->reg_off, ®);
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reg = PARM_GET(parm->width, parm->shift, reg);
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debug("%s: parent of %ld is %d (%d)\n",
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@@ -494,7 +494,6 @@ static ulong meson_mux_set_parent(struct clk *clk, unsigned long id,
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unsigned int new_index = -EINVAL;
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struct parm *parm;
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int *parents;
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- u32 reg;
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int i;
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if (IS_ERR_VALUE(cur_parent))
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@@ -546,9 +545,8 @@ static ulong meson_mux_set_parent(struct clk *clk, unsigned long id,
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debug("%s: new index of %ld is %d\n", __func__, id, new_index);
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- reg = readl(priv->addr + parm->reg_off);
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- writel(PARM_SET(parm->width, parm->shift, reg, new_index),
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- priv->addr + parm->reg_off);
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+ regmap_update_bits(priv->map, parm->reg_off, SETPMASK(parm->width, parm->shift),
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+ new_index << parm->shift);
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debug("%s: new parent of %ld is %ld\n",
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__func__, id, meson_mux_get_parent(clk, id));
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@@ -570,7 +568,7 @@ static unsigned long meson_clk81_get_rate(struct clk *clk)
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{
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struct meson_clk *priv = dev_get_priv(clk->dev);
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unsigned long parent_rate;
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- u32 reg;
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+ uint reg;
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int parents[] = {
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-1,
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-1,
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@@ -583,7 +581,7 @@ static unsigned long meson_clk81_get_rate(struct clk *clk)
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};
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/* mux */
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- reg = readl(priv->addr + HHI_MPEG_CLK_CNTL);
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+ regmap_read(priv->map, HHI_MPEG_CLK_CNTL, ®);
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reg = (reg >> 12) & 7;
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switch (reg) {
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@@ -597,7 +595,7 @@ static unsigned long meson_clk81_get_rate(struct clk *clk)
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}
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/* divider */
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- reg = readl(priv->addr + HHI_MPEG_CLK_CNTL);
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+ regmap_read(priv->map, HHI_MPEG_CLK_CNTL, ®);
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reg = reg & ((1 << 7) - 1);
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/* clk81 divider is zero based */
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@@ -641,8 +639,9 @@ static ulong meson_mpll_get_rate(struct clk *clk, unsigned long id)
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{
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struct meson_clk *priv = dev_get_priv(clk->dev);
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struct parm *psdm, *pn2;
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- unsigned long reg, sdm, n2;
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+ unsigned long sdm, n2;
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unsigned long parent_rate;
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+ uint reg;
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switch (id) {
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case CLKID_MPLL0:
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@@ -665,10 +664,10 @@ static ulong meson_mpll_get_rate(struct clk *clk, unsigned long id)
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if (IS_ERR_VALUE(parent_rate))
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return parent_rate;
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- reg = readl(priv->addr + psdm->reg_off);
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+ regmap_read(priv->map, psdm->reg_off, ®);
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sdm = PARM_GET(psdm->width, psdm->shift, reg);
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- reg = readl(priv->addr + pn2->reg_off);
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+ regmap_read(priv->map, pn2->reg_off, ®);
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n2 = PARM_GET(pn2->width, pn2->shift, reg);
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return mpll_rate_from_params(parent_rate, sdm, n2);
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@@ -692,7 +691,7 @@ static ulong meson_pll_get_rate(struct clk *clk, unsigned long id)
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struct parm *pm, *pn, *pod;
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unsigned long parent_rate_mhz = XTAL_RATE / 1000000;
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u16 n, m, od;
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- u32 reg;
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+ uint reg;
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switch (id) {
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case CLKID_FIXED_PLL:
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@@ -709,13 +708,13 @@ static ulong meson_pll_get_rate(struct clk *clk, unsigned long id)
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return -ENOENT;
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}
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- reg = readl(priv->addr + pn->reg_off);
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+ regmap_read(priv->map, pn->reg_off, ®);
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n = PARM_GET(pn->width, pn->shift, reg);
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- reg = readl(priv->addr + pm->reg_off);
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+ regmap_read(priv->map, pm->reg_off, ®);
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m = PARM_GET(pm->width, pm->shift, reg);
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- reg = readl(priv->addr + pod->reg_off);
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+ regmap_read(priv->map, pod->reg_off, ®);
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od = PARM_GET(pod->width, pod->shift, reg);
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return ((parent_rate_mhz * m / n) >> od) * 1000000;
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@@ -876,8 +875,8 @@ static ulong meson_clk_set_rate(struct clk *clk, ulong rate)
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if (IS_ERR_VALUE(ret))
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return ret;
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- printf("clock %lu has new rate %lu\n", clk->id,
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- meson_clk_get_rate_by_id(clk, clk->id));
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+ debug("clock %lu has new rate %lu\n", clk->id,
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+ meson_clk_get_rate_by_id(clk, clk->id));
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return 0;
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}
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@@ -886,9 +885,11 @@ static int meson_clk_probe(struct udevice *dev)
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{
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struct meson_clk *priv = dev_get_priv(dev);
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- priv->addr = dev_read_addr_ptr(dev);
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+ priv->map = syscon_node_to_regmap(dev_get_parent(dev)->node);
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+ if (IS_ERR(priv->map))
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+ return PTR_ERR(priv->map);
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- debug("meson-clk: probed at addr %p\n", priv->addr);
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+ debug("meson-clk: probed\n");
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return 0;
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}
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