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@@ -67,8 +67,9 @@
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compatible = "allwinner,simple-framebuffer",
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"simple-framebuffer";
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allwinner,pipeline = "de_be0-lcd0-hdmi";
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- clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
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- <&ahb_gates 44>, <&dram_gates 26>;
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+ clocks = <&ahb_gates 36>, <&ahb_gates 43>,
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+ <&ahb_gates 44>, <&de_be0_clk>,
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+ <&tcon0_ch1_clk>, <&dram_gates 26>;
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status = "disabled";
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};
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@@ -76,7 +77,8 @@
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compatible = "allwinner,simple-framebuffer",
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"simple-framebuffer";
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allwinner,pipeline = "de_be0-lcd0";
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- clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>,
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+ clocks = <&ahb_gates 36>, <&ahb_gates 44>,
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+ <&de_be0_clk>, <&tcon0_ch0_clk>,
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<&dram_gates 26>;
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status = "disabled";
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};
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@@ -85,8 +87,10 @@
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compatible = "allwinner,simple-framebuffer",
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"simple-framebuffer";
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allwinner,pipeline = "de_be0-lcd0-tve0";
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- clocks = <&pll5 1>, <&ahb_gates 34>, <&ahb_gates 36>,
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- <&ahb_gates 44>, <&dram_gates 26>;
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+ clocks = <&ahb_gates 34>, <&ahb_gates 36>,
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+ <&ahb_gates 44>,
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+ <&de_be0_clk>, <&tcon0_ch1_clk>,
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+ <&dram_gates 5>, <&dram_gates 26>;
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status = "disabled";
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};
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};
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@@ -186,6 +190,15 @@
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clock-output-names = "osc24M";
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};
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+ osc3M: osc3M_clk {
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+ #clock-cells = <0>;
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+ compatible = "fixed-factor-clock";
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+ clock-div = <8>;
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+ clock-mult = <1>;
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+ clocks = <&osc24M>;
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+ clock-output-names = "osc3M";
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+ };
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+
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osc32k: clk@0 {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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@@ -210,6 +223,23 @@
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"pll2-4x", "pll2-8x";
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};
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+ pll3: clk@01c20010 {
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+ #clock-cells = <0>;
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+ compatible = "allwinner,sun4i-a10-pll3-clk";
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+ reg = <0x01c20010 0x4>;
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+ clocks = <&osc3M>;
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+ clock-output-names = "pll3";
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+ };
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+
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+ pll3x2: pll3x2_clk {
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+ #clock-cells = <0>;
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+ compatible = "fixed-factor-clock";
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+ clocks = <&pll3>;
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+ clock-div = <1>;
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+ clock-mult = <2>;
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+ clock-output-names = "pll3-2x";
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+ };
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+
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pll4: clk@01c20018 {
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#clock-cells = <0>;
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compatible = "allwinner,sun7i-a20-pll4-clk";
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@@ -235,6 +265,23 @@
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"pll6_div_4";
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};
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+ pll7: clk@01c20030 {
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+ #clock-cells = <0>;
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+ compatible = "allwinner,sun4i-a10-pll3-clk";
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+ reg = <0x01c20030 0x4>;
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+ clocks = <&osc3M>;
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+ clock-output-names = "pll7";
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+ };
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+
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+ pll7x2: pll7x2_clk {
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+ #clock-cells = <0>;
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+ compatible = "fixed-factor-clock";
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+ clocks = <&pll7>;
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+ clock-div = <1>;
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+ clock-mult = <2>;
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+ clock-output-names = "pll7-2x";
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+ };
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+
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pll8: clk@01c20040 {
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#clock-cells = <0>;
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compatible = "allwinner,sun7i-a20-pll4-clk";
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@@ -324,9 +371,9 @@
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<5>, <6>, <7>,
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<8>, <10>;
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clock-output-names = "apb0_codec", "apb0_spdif",
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- "apb0_ac97", "apb0_iis0", "apb0_iis1",
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+ "apb0_ac97", "apb0_i2s0", "apb0_i2s1",
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"apb0_pio", "apb0_ir0", "apb0_ir1",
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- "apb0_iis2", "apb0_keypad";
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+ "apb0_i2s2", "apb0_keypad";
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};
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apb1: clk@01c20058 {
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@@ -476,6 +523,39 @@
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clock-output-names = "ir1";
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};
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+ i2s0_clk: clk@01c200b8 {
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+ #clock-cells = <0>;
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+ compatible = "allwinner,sun4i-a10-mod1-clk";
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+ reg = <0x01c200b8 0x4>;
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+ clocks = <&pll2 SUN4I_A10_PLL2_8X>,
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+ <&pll2 SUN4I_A10_PLL2_4X>,
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+ <&pll2 SUN4I_A10_PLL2_2X>,
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+ <&pll2 SUN4I_A10_PLL2_1X>;
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+ clock-output-names = "i2s0";
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+ };
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+
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+ ac97_clk: clk@01c200bc {
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+ #clock-cells = <0>;
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+ compatible = "allwinner,sun4i-a10-mod1-clk";
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+ reg = <0x01c200bc 0x4>;
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+ clocks = <&pll2 SUN4I_A10_PLL2_8X>,
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+ <&pll2 SUN4I_A10_PLL2_4X>,
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+ <&pll2 SUN4I_A10_PLL2_2X>,
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+ <&pll2 SUN4I_A10_PLL2_1X>;
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+ clock-output-names = "ac97";
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+ };
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+
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+ spdif_clk: clk@01c200c0 {
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+ #clock-cells = <0>;
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+ compatible = "allwinner,sun4i-a10-mod1-clk";
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+ reg = <0x01c200c0 0x4>;
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+ clocks = <&pll2 SUN4I_A10_PLL2_8X>,
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+ <&pll2 SUN4I_A10_PLL2_4X>,
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+ <&pll2 SUN4I_A10_PLL2_2X>,
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+ <&pll2 SUN4I_A10_PLL2_1X>;
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+ clock-output-names = "spdif";
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+ };
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+
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keypad_clk: clk@01c200c4 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-mod0-clk";
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@@ -502,6 +582,28 @@
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clock-output-names = "spi3";
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};
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+ i2s1_clk: clk@01c200d8 {
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+ #clock-cells = <0>;
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+ compatible = "allwinner,sun4i-a10-mod1-clk";
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+ reg = <0x01c200d8 0x4>;
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+ clocks = <&pll2 SUN4I_A10_PLL2_8X>,
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+ <&pll2 SUN4I_A10_PLL2_4X>,
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+ <&pll2 SUN4I_A10_PLL2_2X>,
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+ <&pll2 SUN4I_A10_PLL2_1X>;
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+ clock-output-names = "i2s1";
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+ };
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+
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+ i2s2_clk: clk@01c200dc {
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+ #clock-cells = <0>;
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+ compatible = "allwinner,sun4i-a10-mod1-clk";
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+ reg = <0x01c200dc 0x4>;
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+ clocks = <&pll2 SUN4I_A10_PLL2_8X>,
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+ <&pll2 SUN4I_A10_PLL2_4X>,
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+ <&pll2 SUN4I_A10_PLL2_2X>,
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+ <&pll2 SUN4I_A10_PLL2_1X>;
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+ clock-output-names = "i2s2";
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+ };
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+
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dram_gates: clk@01c20100 {
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#clock-cells = <1>;
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compatible = "allwinner,sun4i-a10-dram-gates-clk";
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@@ -527,6 +629,80 @@
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"dram_de_mp", "dram_ace";
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};
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+ de_be0_clk: clk@01c20104 {
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+ #clock-cells = <0>;
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+ #reset-cells = <0>;
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+ compatible = "allwinner,sun4i-a10-display-clk";
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+ reg = <0x01c20104 0x4>;
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+ clocks = <&pll3>, <&pll7>, <&pll5 1>;
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+ clock-output-names = "de-be0";
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+ };
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+
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+ de_be1_clk: clk@01c20108 {
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+ #clock-cells = <0>;
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+ #reset-cells = <0>;
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+ compatible = "allwinner,sun4i-a10-display-clk";
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+ reg = <0x01c20108 0x4>;
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+ clocks = <&pll3>, <&pll7>, <&pll5 1>;
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+ clock-output-names = "de-be1";
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+ };
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+
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+ de_fe0_clk: clk@01c2010c {
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+ #clock-cells = <0>;
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+ #reset-cells = <0>;
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+ compatible = "allwinner,sun4i-a10-display-clk";
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+ reg = <0x01c2010c 0x4>;
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+ clocks = <&pll3>, <&pll7>, <&pll5 1>;
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+ clock-output-names = "de-fe0";
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+ };
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+
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+ de_fe1_clk: clk@01c20110 {
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+ #clock-cells = <0>;
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+ #reset-cells = <0>;
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+ compatible = "allwinner,sun4i-a10-display-clk";
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+ reg = <0x01c20110 0x4>;
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+ clocks = <&pll3>, <&pll7>, <&pll5 1>;
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+ clock-output-names = "de-fe1";
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+ };
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+
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+ tcon0_ch0_clk: clk@01c20118 {
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+ #clock-cells = <0>;
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+ #reset-cells = <1>;
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+ compatible = "allwinner,sun4i-a10-tcon-ch0-clk";
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+ reg = <0x01c20118 0x4>;
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+ clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
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+ clock-output-names = "tcon0-ch0-sclk";
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+
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+ };
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+
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+ tcon1_ch0_clk: clk@01c2011c {
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+ #clock-cells = <0>;
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+ #reset-cells = <1>;
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+ compatible = "allwinner,sun4i-a10-tcon-ch1-clk";
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+ reg = <0x01c2011c 0x4>;
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+ clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
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+ clock-output-names = "tcon1-ch0-sclk";
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+
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+ };
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+
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+ tcon0_ch1_clk: clk@01c2012c {
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+ #clock-cells = <0>;
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+ compatible = "allwinner,sun4i-a10-tcon-ch0-clk";
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+ reg = <0x01c2012c 0x4>;
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+ clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
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+ clock-output-names = "tcon0-ch1-sclk";
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+
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+ };
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+
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+ tcon1_ch1_clk: clk@01c20130 {
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+ #clock-cells = <0>;
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+ compatible = "allwinner,sun4i-a10-tcon-ch1-clk";
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+ reg = <0x01c20130 0x4>;
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+ clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
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+ clock-output-names = "tcon1-ch1-sclk";
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+
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+ };
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+
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ve_clk: clk@01c2013c {
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#clock-cells = <0>;
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#reset-cells = <0>;
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@@ -670,6 +846,19 @@
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#dma-cells = <2>;
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};
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+ nfc: nand@01c03000 {
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+ compatible = "allwinner,sun4i-a10-nand";
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+ reg = <0x01c03000 0x1000>;
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+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&ahb_gates 13>, <&nand_clk>;
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+ clock-names = "ahb", "mod";
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+ dmas = <&dma SUN4I_DMA_DEDICATED 3>;
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+ dma-names = "rxtx";
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+ status = "disabled";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ };
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+
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spi0: spi@01c05000 {
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compatible = "allwinner,sun4i-a10-spi";
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reg = <0x01c05000 0x1000>;
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@@ -716,7 +905,8 @@
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};
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mmc0: mmc@01c0f000 {
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- compatible = "allwinner,sun5i-a13-mmc";
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+ compatible = "allwinner,sun7i-a20-mmc",
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+ "allwinner,sun5i-a13-mmc";
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reg = <0x01c0f000 0x1000>;
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clocks = <&ahb_gates 8>,
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<&mmc0_clk 0>,
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@@ -733,7 +923,8 @@
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};
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mmc1: mmc@01c10000 {
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- compatible = "allwinner,sun5i-a13-mmc";
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+ compatible = "allwinner,sun7i-a20-mmc",
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+ "allwinner,sun5i-a13-mmc";
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reg = <0x01c10000 0x1000>;
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clocks = <&ahb_gates 9>,
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<&mmc1_clk 0>,
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@@ -750,7 +941,8 @@
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};
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mmc2: mmc@01c11000 {
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- compatible = "allwinner,sun5i-a13-mmc";
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+ compatible = "allwinner,sun7i-a20-mmc",
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+ "allwinner,sun5i-a13-mmc";
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reg = <0x01c11000 0x1000>;
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clocks = <&ahb_gates 10>,
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<&mmc2_clk 0>,
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@@ -767,7 +959,8 @@
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};
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mmc3: mmc@01c12000 {
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- compatible = "allwinner,sun5i-a13-mmc";
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+ compatible = "allwinner,sun7i-a20-mmc",
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+ "allwinner,sun5i-a13-mmc";
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reg = <0x01c12000 0x1000>;
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clocks = <&ahb_gates 11>,
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<&mmc3_clk 0>,
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@@ -902,160 +1095,177 @@
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#interrupt-cells = <3>;
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#gpio-cells = <3>;
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- pwm0_pins_a: pwm0@0 {
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- allwinner,pins = "PB2";
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- allwinner,function = "pwm";
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+ clk_out_a_pins_a: clk_out_a@0 {
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+ allwinner,pins = "PI12";
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+ allwinner,function = "clk_out_a";
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allwinner,drive = <SUN4I_PINCTRL_10_MA>;
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allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
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};
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- pwm1_pins_a: pwm1@0 {
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- allwinner,pins = "PI3";
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- allwinner,function = "pwm";
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+ clk_out_b_pins_a: clk_out_b@0 {
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+ allwinner,pins = "PI13";
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+ allwinner,function = "clk_out_b";
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allwinner,drive = <SUN4I_PINCTRL_10_MA>;
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allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
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};
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- uart0_pins_a: uart0@0 {
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- allwinner,pins = "PB22", "PB23";
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- allwinner,function = "uart0";
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+ emac_pins_a: emac0@0 {
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+ allwinner,pins = "PA0", "PA1", "PA2",
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+ "PA3", "PA4", "PA5", "PA6",
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+ "PA7", "PA8", "PA9", "PA10",
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+ "PA11", "PA12", "PA13", "PA14",
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+ "PA15", "PA16";
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+ allwinner,function = "emac";
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allwinner,drive = <SUN4I_PINCTRL_10_MA>;
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allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
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};
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- uart2_pins_a: uart2@0 {
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- allwinner,pins = "PI16", "PI17", "PI18", "PI19";
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- allwinner,function = "uart2";
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+ gmac_pins_mii_a: gmac_mii@0 {
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+ allwinner,pins = "PA0", "PA1", "PA2",
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+ "PA3", "PA4", "PA5", "PA6",
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+ "PA7", "PA8", "PA9", "PA10",
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+ "PA11", "PA12", "PA13", "PA14",
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+ "PA15", "PA16";
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+ allwinner,function = "gmac";
|
|
|
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
|
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
|
};
|
|
|
|
|
|
- uart3_pins_a: uart3@0 {
|
|
|
- allwinner,pins = "PG6", "PG7", "PG8", "PG9";
|
|
|
- allwinner,function = "uart3";
|
|
|
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
|
+ gmac_pins_rgmii_a: gmac_rgmii@0 {
|
|
|
+ allwinner,pins = "PA0", "PA1", "PA2",
|
|
|
+ "PA3", "PA4", "PA5", "PA6",
|
|
|
+ "PA7", "PA8", "PA10",
|
|
|
+ "PA11", "PA12", "PA13",
|
|
|
+ "PA15", "PA16";
|
|
|
+ allwinner,function = "gmac";
|
|
|
+ /*
|
|
|
+ * data lines in RGMII mode use DDR mode
|
|
|
+ * and need a higher signal drive strength
|
|
|
+ */
|
|
|
+ allwinner,drive = <SUN4I_PINCTRL_40_MA>;
|
|
|
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
|
};
|
|
|
|
|
|
- uart3_pins_b: uart3@1 {
|
|
|
- allwinner,pins = "PH0", "PH1";
|
|
|
- allwinner,function = "uart3";
|
|
|
+ i2c0_pins_a: i2c0@0 {
|
|
|
+ allwinner,pins = "PB0", "PB1";
|
|
|
+ allwinner,function = "i2c0";
|
|
|
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
|
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
|
};
|
|
|
|
|
|
- uart4_pins_a: uart4@0 {
|
|
|
- allwinner,pins = "PG10", "PG11";
|
|
|
- allwinner,function = "uart4";
|
|
|
+ i2c1_pins_a: i2c1@0 {
|
|
|
+ allwinner,pins = "PB18", "PB19";
|
|
|
+ allwinner,function = "i2c1";
|
|
|
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
|
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
|
};
|
|
|
|
|
|
- uart4_pins_b: uart4@1 {
|
|
|
- allwinner,pins = "PH4", "PH5";
|
|
|
- allwinner,function = "uart4";
|
|
|
+ i2c2_pins_a: i2c2@0 {
|
|
|
+ allwinner,pins = "PB20", "PB21";
|
|
|
+ allwinner,function = "i2c2";
|
|
|
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
|
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
|
};
|
|
|
|
|
|
- uart5_pins_a: uart5@0 {
|
|
|
- allwinner,pins = "PI10", "PI11";
|
|
|
- allwinner,function = "uart5";
|
|
|
+ i2c3_pins_a: i2c3@0 {
|
|
|
+ allwinner,pins = "PI0", "PI1";
|
|
|
+ allwinner,function = "i2c3";
|
|
|
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
|
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
|
};
|
|
|
|
|
|
- uart6_pins_a: uart6@0 {
|
|
|
- allwinner,pins = "PI12", "PI13";
|
|
|
- allwinner,function = "uart6";
|
|
|
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
|
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
|
+ ir0_rx_pins_a: ir0@0 {
|
|
|
+ allwinner,pins = "PB4";
|
|
|
+ allwinner,function = "ir0";
|
|
|
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
|
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
|
};
|
|
|
|
|
|
- uart7_pins_a: uart7@0 {
|
|
|
- allwinner,pins = "PI20", "PI21";
|
|
|
- allwinner,function = "uart7";
|
|
|
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
|
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
|
+ ir0_tx_pins_a: ir0@1 {
|
|
|
+ allwinner,pins = "PB3";
|
|
|
+ allwinner,function = "ir0";
|
|
|
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
|
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
|
};
|
|
|
|
|
|
- i2c0_pins_a: i2c0@0 {
|
|
|
- allwinner,pins = "PB0", "PB1";
|
|
|
- allwinner,function = "i2c0";
|
|
|
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
|
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
|
+ ir1_rx_pins_a: ir1@0 {
|
|
|
+ allwinner,pins = "PB23";
|
|
|
+ allwinner,function = "ir1";
|
|
|
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
|
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
|
};
|
|
|
|
|
|
- i2c1_pins_a: i2c1@0 {
|
|
|
- allwinner,pins = "PB18", "PB19";
|
|
|
- allwinner,function = "i2c1";
|
|
|
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
|
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
|
+ ir1_tx_pins_a: ir1@1 {
|
|
|
+ allwinner,pins = "PB22";
|
|
|
+ allwinner,function = "ir1";
|
|
|
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
|
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
|
};
|
|
|
|
|
|
- i2c2_pins_a: i2c2@0 {
|
|
|
- allwinner,pins = "PB20", "PB21";
|
|
|
- allwinner,function = "i2c2";
|
|
|
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
|
+ mmc0_pins_a: mmc0@0 {
|
|
|
+ allwinner,pins = "PF0", "PF1", "PF2",
|
|
|
+ "PF3", "PF4", "PF5";
|
|
|
+ allwinner,function = "mmc0";
|
|
|
+ allwinner,drive = <SUN4I_PINCTRL_30_MA>;
|
|
|
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
|
};
|
|
|
|
|
|
- i2c3_pins_a: i2c3@0 {
|
|
|
- allwinner,pins = "PI0", "PI1";
|
|
|
- allwinner,function = "i2c3";
|
|
|
+ mmc0_cd_pin_reference_design: mmc0_cd_pin@0 {
|
|
|
+ allwinner,pins = "PH1";
|
|
|
+ allwinner,function = "gpio_in";
|
|
|
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
|
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
|
|
|
+ };
|
|
|
+
|
|
|
+ mmc2_pins_a: mmc2@0 {
|
|
|
+ allwinner,pins = "PC6", "PC7", "PC8",
|
|
|
+ "PC9", "PC10", "PC11";
|
|
|
+ allwinner,function = "mmc2";
|
|
|
+ allwinner,drive = <SUN4I_PINCTRL_30_MA>;
|
|
|
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
|
|
|
+ };
|
|
|
+
|
|
|
+ mmc3_pins_a: mmc3@0 {
|
|
|
+ allwinner,pins = "PI4", "PI5", "PI6",
|
|
|
+ "PI7", "PI8", "PI9";
|
|
|
+ allwinner,function = "mmc3";
|
|
|
+ allwinner,drive = <SUN4I_PINCTRL_30_MA>;
|
|
|
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
|
};
|
|
|
|
|
|
- emac_pins_a: emac0@0 {
|
|
|
- allwinner,pins = "PA0", "PA1", "PA2",
|
|
|
- "PA3", "PA4", "PA5", "PA6",
|
|
|
- "PA7", "PA8", "PA9", "PA10",
|
|
|
- "PA11", "PA12", "PA13", "PA14",
|
|
|
- "PA15", "PA16";
|
|
|
- allwinner,function = "emac";
|
|
|
+ ps20_pins_a: ps20@0 {
|
|
|
+ allwinner,pins = "PI20", "PI21";
|
|
|
+ allwinner,function = "ps2";
|
|
|
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
|
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
|
};
|
|
|
|
|
|
- clk_out_a_pins_a: clk_out_a@0 {
|
|
|
- allwinner,pins = "PI12";
|
|
|
- allwinner,function = "clk_out_a";
|
|
|
+ ps21_pins_a: ps21@0 {
|
|
|
+ allwinner,pins = "PH12", "PH13";
|
|
|
+ allwinner,function = "ps2";
|
|
|
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
|
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
|
};
|
|
|
|
|
|
- clk_out_b_pins_a: clk_out_b@0 {
|
|
|
- allwinner,pins = "PI13";
|
|
|
- allwinner,function = "clk_out_b";
|
|
|
+ pwm0_pins_a: pwm0@0 {
|
|
|
+ allwinner,pins = "PB2";
|
|
|
+ allwinner,function = "pwm";
|
|
|
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
|
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
|
};
|
|
|
|
|
|
- gmac_pins_mii_a: gmac_mii@0 {
|
|
|
- allwinner,pins = "PA0", "PA1", "PA2",
|
|
|
- "PA3", "PA4", "PA5", "PA6",
|
|
|
- "PA7", "PA8", "PA9", "PA10",
|
|
|
- "PA11", "PA12", "PA13", "PA14",
|
|
|
- "PA15", "PA16";
|
|
|
- allwinner,function = "gmac";
|
|
|
+ pwm1_pins_a: pwm1@0 {
|
|
|
+ allwinner,pins = "PI3";
|
|
|
+ allwinner,function = "pwm";
|
|
|
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
|
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
|
};
|
|
|
|
|
|
- gmac_pins_rgmii_a: gmac_rgmii@0 {
|
|
|
- allwinner,pins = "PA0", "PA1", "PA2",
|
|
|
- "PA3", "PA4", "PA5", "PA6",
|
|
|
- "PA7", "PA8", "PA10",
|
|
|
- "PA11", "PA12", "PA13",
|
|
|
- "PA15", "PA16";
|
|
|
- allwinner,function = "gmac";
|
|
|
- /*
|
|
|
- * data lines in RGMII mode use DDR mode
|
|
|
- * and need a higher signal drive strength
|
|
|
- */
|
|
|
- allwinner,drive = <SUN4I_PINCTRL_40_MA>;
|
|
|
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
|
+ spdif_tx_pins_a: spdif@0 {
|
|
|
+ allwinner,pins = "PB13";
|
|
|
+ allwinner,function = "spdif";
|
|
|
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
|
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
|
|
|
};
|
|
|
|
|
|
spi0_pins_a: spi0@0 {
|
|
@@ -1121,75 +1331,65 @@
|
|
|
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
|
};
|
|
|
|
|
|
- mmc0_pins_a: mmc0@0 {
|
|
|
- allwinner,pins = "PF0", "PF1", "PF2",
|
|
|
- "PF3", "PF4", "PF5";
|
|
|
- allwinner,function = "mmc0";
|
|
|
- allwinner,drive = <SUN4I_PINCTRL_30_MA>;
|
|
|
+ uart0_pins_a: uart0@0 {
|
|
|
+ allwinner,pins = "PB22", "PB23";
|
|
|
+ allwinner,function = "uart0";
|
|
|
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
|
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
|
};
|
|
|
|
|
|
- mmc0_cd_pin_reference_design: mmc0_cd_pin@0 {
|
|
|
- allwinner,pins = "PH1";
|
|
|
- allwinner,function = "gpio_in";
|
|
|
+ uart2_pins_a: uart2@0 {
|
|
|
+ allwinner,pins = "PI16", "PI17", "PI18", "PI19";
|
|
|
+ allwinner,function = "uart2";
|
|
|
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
|
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
|
|
|
- };
|
|
|
-
|
|
|
- mmc2_pins_a: mmc2@0 {
|
|
|
- allwinner,pins = "PC6", "PC7", "PC8",
|
|
|
- "PC9", "PC10", "PC11";
|
|
|
- allwinner,function = "mmc2";
|
|
|
- allwinner,drive = <SUN4I_PINCTRL_30_MA>;
|
|
|
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
|
|
|
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
|
};
|
|
|
|
|
|
- mmc3_pins_a: mmc3@0 {
|
|
|
- allwinner,pins = "PI4", "PI5", "PI6",
|
|
|
- "PI7", "PI8", "PI9";
|
|
|
- allwinner,function = "mmc3";
|
|
|
- allwinner,drive = <SUN4I_PINCTRL_30_MA>;
|
|
|
+ uart3_pins_a: uart3@0 {
|
|
|
+ allwinner,pins = "PG6", "PG7", "PG8", "PG9";
|
|
|
+ allwinner,function = "uart3";
|
|
|
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
|
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
|
};
|
|
|
|
|
|
- ir0_rx_pins_a: ir0@0 {
|
|
|
- allwinner,pins = "PB4";
|
|
|
- allwinner,function = "ir0";
|
|
|
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
|
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
|
+ uart3_pins_b: uart3@1 {
|
|
|
+ allwinner,pins = "PH0", "PH1";
|
|
|
+ allwinner,function = "uart3";
|
|
|
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
|
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
|
};
|
|
|
|
|
|
- ir0_tx_pins_a: ir0@1 {
|
|
|
- allwinner,pins = "PB3";
|
|
|
- allwinner,function = "ir0";
|
|
|
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
|
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
|
+ uart4_pins_a: uart4@0 {
|
|
|
+ allwinner,pins = "PG10", "PG11";
|
|
|
+ allwinner,function = "uart4";
|
|
|
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
|
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
|
};
|
|
|
|
|
|
- ir1_rx_pins_a: ir1@0 {
|
|
|
- allwinner,pins = "PB23";
|
|
|
- allwinner,function = "ir1";
|
|
|
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
|
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
|
+ uart4_pins_b: uart4@1 {
|
|
|
+ allwinner,pins = "PH4", "PH5";
|
|
|
+ allwinner,function = "uart4";
|
|
|
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
|
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
|
};
|
|
|
|
|
|
- ir1_tx_pins_a: ir1@1 {
|
|
|
- allwinner,pins = "PB22";
|
|
|
- allwinner,function = "ir1";
|
|
|
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
|
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
|
+ uart5_pins_a: uart5@0 {
|
|
|
+ allwinner,pins = "PI10", "PI11";
|
|
|
+ allwinner,function = "uart5";
|
|
|
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
|
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
|
};
|
|
|
|
|
|
- ps20_pins_a: ps20@0 {
|
|
|
- allwinner,pins = "PI20", "PI21";
|
|
|
- allwinner,function = "ps2";
|
|
|
+ uart6_pins_a: uart6@0 {
|
|
|
+ allwinner,pins = "PI12", "PI13";
|
|
|
+ allwinner,function = "uart6";
|
|
|
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
|
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
|
};
|
|
|
|
|
|
- ps21_pins_a: ps21@0 {
|
|
|
- allwinner,pins = "PH12", "PH13";
|
|
|
- allwinner,function = "ps2";
|
|
|
+ uart7_pins_a: uart7@0 {
|
|
|
+ allwinner,pins = "PI20", "PI21";
|
|
|
+ allwinner,function = "uart7";
|
|
|
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
|
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
|
};
|
|
@@ -1226,6 +1426,19 @@
|
|
|
status = "disabled";
|
|
|
};
|
|
|
|
|
|
+ spdif: spdif@01c21000 {
|
|
|
+ #sound-dai-cells = <0>;
|
|
|
+ compatible = "allwinner,sun4i-a10-spdif";
|
|
|
+ reg = <0x01c21000 0x400>;
|
|
|
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ clocks = <&apb0_gates 1>, <&spdif_clk>;
|
|
|
+ clock-names = "apb", "spdif";
|
|
|
+ dmas = <&dma SUN4I_DMA_NORMAL 2>,
|
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|
+ <&dma SUN4I_DMA_NORMAL 2>;
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|
|
+ dma-names = "rx", "tx";
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|
|
+ status = "disabled";
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|
|
+ };
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|
|
+
|
|
|
ir0: ir@01c21800 {
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|
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compatible = "allwinner,sun4i-a10-ir";
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|
|
clocks = <&apb0_gates 6>, <&ir0_clk>;
|
|
@@ -1244,6 +1457,32 @@
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|
status = "disabled";
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|
};
|
|
|
|
|
|
+ i2s1: i2s@01c22000 {
|
|
|
+ #sound-dai-cells = <0>;
|
|
|
+ compatible = "allwinner,sun4i-a10-i2s";
|
|
|
+ reg = <0x01c22000 0x400>;
|
|
|
+ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ clocks = <&apb0_gates 4>, <&i2s1_clk>;
|
|
|
+ clock-names = "apb", "mod";
|
|
|
+ dmas = <&dma SUN4I_DMA_NORMAL 4>,
|
|
|
+ <&dma SUN4I_DMA_NORMAL 4>;
|
|
|
+ dma-names = "rx", "tx";
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ i2s0: i2s@01c22400 {
|
|
|
+ #sound-dai-cells = <0>;
|
|
|
+ compatible = "allwinner,sun4i-a10-i2s";
|
|
|
+ reg = <0x01c22400 0x400>;
|
|
|
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ clocks = <&apb0_gates 3>, <&i2s0_clk>;
|
|
|
+ clock-names = "apb", "mod";
|
|
|
+ dmas = <&dma SUN4I_DMA_NORMAL 3>,
|
|
|
+ <&dma SUN4I_DMA_NORMAL 3>;
|
|
|
+ dma-names = "rx", "tx";
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
lradc: lradc@01c22800 {
|
|
|
compatible = "allwinner,sun4i-a10-lradc-keys";
|
|
|
reg = <0x01c22800 0x100>;
|
|
@@ -1269,6 +1508,19 @@
|
|
|
reg = <0x01c23800 0x200>;
|
|
|
};
|
|
|
|
|
|
+ i2s2: i2s@01c24400 {
|
|
|
+ #sound-dai-cells = <0>;
|
|
|
+ compatible = "allwinner,sun4i-a10-i2s";
|
|
|
+ reg = <0x01c24400 0x400>;
|
|
|
+ interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ clocks = <&apb0_gates 8>, <&i2s2_clk>;
|
|
|
+ clock-names = "apb", "mod";
|
|
|
+ dmas = <&dma SUN4I_DMA_NORMAL 6>,
|
|
|
+ <&dma SUN4I_DMA_NORMAL 6>;
|
|
|
+ dma-names = "rx", "tx";
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
rtp: rtp@01c25000 {
|
|
|
compatible = "allwinner,sun5i-a13-ts";
|
|
|
reg = <0x01c25000 0x100>;
|