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@@ -121,24 +121,25 @@ void ls_pcie_atu_inbound_set(struct ls_pcie *pcie, u32 pf, u32 vf_flag,
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PCIE_ATU_BAR_NUM(bar), PCIE_ATU_CR2);
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}
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-void ls_pcie_dump_atu(struct ls_pcie *pcie)
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+void ls_pcie_dump_atu(struct ls_pcie *pcie, u32 win_num, u32 type)
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{
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- int i;
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+ int win_idx;
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- for (i = 0; i < PCIE_ATU_REGION_NUM; i++) {
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- dbi_writel(pcie, PCIE_ATU_REGION_OUTBOUND | i,
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- PCIE_ATU_VIEWPORT);
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- debug("iATU%d:\n", i);
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+ for (win_idx = 0; win_idx < win_num; win_idx++) {
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+ dbi_writel(pcie, type | win_idx, PCIE_ATU_VIEWPORT);
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+ debug("iATU%d:\n", win_idx);
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debug("\tLOWER PHYS 0x%08x\n",
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dbi_readl(pcie, PCIE_ATU_LOWER_BASE));
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debug("\tUPPER PHYS 0x%08x\n",
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dbi_readl(pcie, PCIE_ATU_UPPER_BASE));
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- debug("\tLOWER BUS 0x%08x\n",
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- dbi_readl(pcie, PCIE_ATU_LOWER_TARGET));
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- debug("\tUPPER BUS 0x%08x\n",
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- dbi_readl(pcie, PCIE_ATU_UPPER_TARGET));
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- debug("\tLIMIT 0x%08x\n",
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- dbi_readl(pcie, PCIE_ATU_LIMIT));
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+ if (type == PCIE_ATU_REGION_OUTBOUND) {
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+ debug("\tLOWER BUS 0x%08x\n",
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+ dbi_readl(pcie, PCIE_ATU_LOWER_TARGET));
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+ debug("\tUPPER BUS 0x%08x\n",
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+ dbi_readl(pcie, PCIE_ATU_UPPER_TARGET));
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+ debug("\tLIMIT 0x%08x\n",
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+ dbi_readl(pcie, PCIE_ATU_LIMIT));
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+ }
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debug("\tCR1 0x%08x\n",
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dbi_readl(pcie, PCIE_ATU_CR1));
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debug("\tCR2 0x%08x\n",
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