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@@ -80,6 +80,11 @@ static void configure_mr(int nr, u32 cs)
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*/
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void config_sdram_emif4d5(const struct emif_regs *regs, int nr)
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{
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+#ifdef CONFIG_AM43XX
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+ struct prm_device_inst *prm_device =
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+ (struct prm_device_inst *)PRM_DEVICE_INST;
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+#endif
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+
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writel(0xA0, &emif_reg[nr]->emif_pwr_mgmt_ctrl);
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writel(0xA0, &emif_reg[nr]->emif_pwr_mgmt_ctrl_shdw);
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writel(regs->zq_config, &emif_reg[nr]->emif_zq_config);
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@@ -126,6 +131,15 @@ void config_sdram_emif4d5(const struct emif_regs *regs, int nr)
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writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
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writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
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+#ifdef CONFIG_AM43XX
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+ /*
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+ * Disable EMIF_DEVOFF
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+ * -> Cold Boot: This is just rewriting the default register value.
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+ * -> RTC Resume: Must disable DEVOFF before leveling.
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+ */
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+ writel(0, &prm_device->emif_ctrl);
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+#endif
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+
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/* Perform hardware leveling for DDR3 */
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if (emif_sdram_type(regs->sdram_config) == EMIF_SDRAM_TYPE_DDR3) {
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writel(readl(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_36) |
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