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@@ -331,5 +331,163 @@ struct bootrom_sw_info {
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#define ROM_SW_INFO_ADDR is_soc_rev(CHIP_REV_1_0) ? \
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(struct bootrom_sw_info **)ROM_SW_INFO_ADDR_A0 : \
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(struct bootrom_sw_info **)ROM_SW_INFO_ADDR_B0
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+
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+struct gpc_reg {
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+ u32 lpcr_bsc;
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+ u32 lpcr_ad;
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+ u32 lpcr_cpu1;
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+ u32 lpcr_cpu2;
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+ u32 lpcr_cpu3;
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+ u32 slpcr;
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+ u32 mst_cpu_mapping;
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+ u32 mmdc_cpu_mapping;
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+ u32 mlpcr;
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+ u32 pgc_ack_sel;
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+ u32 pgc_ack_sel_m4;
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+ u32 gpc_misc;
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+ u32 imr1_core0;
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+ u32 imr2_core0;
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+ u32 imr3_core0;
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+ u32 imr4_core0;
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+ u32 imr1_core1;
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+ u32 imr2_core1;
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+ u32 imr3_core1;
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+ u32 imr4_core1;
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+ u32 imr1_cpu1;
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+ u32 imr2_cpu1;
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+ u32 imr3_cpu1;
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+ u32 imr4_cpu1;
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+ u32 imr1_cpu3;
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+ u32 imr2_cpu3;
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+ u32 imr3_cpu3;
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+ u32 imr4_cpu3;
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+ u32 isr1_cpu0;
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+ u32 isr2_cpu0;
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+ u32 isr3_cpu0;
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+ u32 isr4_cpu0;
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+ u32 isr1_cpu1;
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+ u32 isr2_cpu1;
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+ u32 isr3_cpu1;
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+ u32 isr4_cpu1;
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+ u32 isr1_cpu2;
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+ u32 isr2_cpu2;
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+ u32 isr3_cpu2;
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+ u32 isr4_cpu2;
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+ u32 isr1_cpu3;
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+ u32 isr2_cpu3;
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+ u32 isr3_cpu3;
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+ u32 isr4_cpu3;
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+ u32 slt0_cfg;
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+ u32 slt1_cfg;
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+ u32 slt2_cfg;
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+ u32 slt3_cfg;
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+ u32 slt4_cfg;
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+ u32 slt5_cfg;
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+ u32 slt6_cfg;
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+ u32 slt7_cfg;
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+ u32 slt8_cfg;
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+ u32 slt9_cfg;
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+ u32 slt10_cfg;
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+ u32 slt11_cfg;
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+ u32 slt12_cfg;
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+ u32 slt13_cfg;
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+ u32 slt14_cfg;
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+ u32 pgc_cpu_0_1_mapping;
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+ u32 cpu_pgc_up_trg;
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+ u32 mix_pgc_up_trg;
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+ u32 pu_pgc_up_trg;
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+ u32 cpu_pgc_dn_trg;
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+ u32 mix_pgc_dn_trg;
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+ u32 pu_pgc_dn_trg;
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+ u32 lpcr_bsc2;
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+ u32 pgc_cpu_2_3_mapping;
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+ u32 lps_cpu0;
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+ u32 lps_cpu1;
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+ u32 lps_cpu2;
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+ u32 lps_cpu3;
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+ u32 gpc_gpr;
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+ u32 gtor;
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+ u32 debug_addr1;
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+ u32 debug_addr2;
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+ u32 cpu_pgc_up_status1;
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+ u32 mix_pgc_up_status0;
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+ u32 mix_pgc_up_status1;
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+ u32 mix_pgc_up_status2;
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+ u32 m4_mix_pgc_up_status0;
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+ u32 m4_mix_pgc_up_status1;
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+ u32 m4_mix_pgc_up_status2;
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+ u32 pu_pgc_up_status0;
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+ u32 pu_pgc_up_status1;
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+ u32 pu_pgc_up_status2;
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+ u32 m4_pu_pgc_up_status0;
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+ u32 m4_pu_pgc_up_status1;
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+ u32 m4_pu_pgc_up_status2;
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+ u32 a53_lp_io_0;
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+ u32 a53_lp_io_1;
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+ u32 a53_lp_io_2;
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+ u32 cpu_pgc_dn_status1;
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+ u32 mix_pgc_dn_status0;
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+ u32 mix_pgc_dn_status1;
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+ u32 mix_pgc_dn_status2;
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+ u32 m4_mix_pgc_dn_status0;
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+ u32 m4_mix_pgc_dn_status1;
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+ u32 m4_mix_pgc_dn_status2;
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+ u32 pu_pgc_dn_status0;
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+ u32 pu_pgc_dn_status1;
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+ u32 pu_pgc_dn_status2;
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+ u32 m4_pu_pgc_dn_status0;
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+ u32 m4_pu_pgc_dn_status1;
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+ u32 m4_pu_pgc_dn_status2;
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+ u32 res[3];
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+ u32 mix_pdn_flg;
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+ u32 pu_pdn_flg;
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+ u32 m4_mix_pdn_flg;
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+ u32 m4_pu_pdn_flg;
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+ u32 imr1_core2;
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+ u32 imr2_core2;
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+ u32 imr3_core2;
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+ u32 imr4_core2;
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+ u32 imr1_core3;
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+ u32 imr2_core3;
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+ u32 imr3_core3;
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+ u32 imr4_core3;
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+ u32 pgc_ack_sel_pu;
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+ u32 pgc_ack_sel_m4_pu;
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+ u32 slt15_cfg;
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+ u32 slt16_cfg;
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+ u32 slt17_cfg;
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+ u32 slt18_cfg;
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+ u32 slt19_cfg;
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+ u32 gpc_pu_pwrhsk;
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+ u32 slt0_cfg_pu;
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+ u32 slt1_cfg_pu;
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+ u32 slt2_cfg_pu;
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+ u32 slt3_cfg_pu;
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+ u32 slt4_cfg_pu;
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+ u32 slt5_cfg_pu;
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+ u32 slt6_cfg_pu;
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+ u32 slt7_cfg_pu;
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+ u32 slt8_cfg_pu;
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+ u32 slt9_cfg_pu;
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+ u32 slt10_cfg_pu;
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+ u32 slt11_cfg_pu;
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+ u32 slt12_cfg_pu;
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+ u32 slt13_cfg_pu;
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+ u32 slt14_cfg_pu;
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+ u32 slt15_cfg_pu;
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+ u32 slt16_cfg_pu;
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+ u32 slt17_cfg_pu;
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+ u32 slt18_cfg_pu;
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+ u32 slt19_cfg_pu;
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+};
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+
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+struct pgc_reg {
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+ u32 pgcr;
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+ u32 pgpupscr;
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+ u32 pgpdnscr;
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+ u32 pgsr;
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+ u32 pgauxsw;
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+ u32 pgdr;
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+};
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#endif
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#endif
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