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@@ -554,6 +554,47 @@ void scsi_init(void)
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}
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#endif
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+#ifdef CONFIG_USB_XHCI_MVEBU
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+#define USB3_MAX_WINDOWS 4
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+#define USB3_WIN_CTRL(w) (0x0 + ((w) * 8))
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+#define USB3_WIN_BASE(w) (0x4 + ((w) * 8))
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+
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+static void xhci_mvebu_mbus_config(void __iomem *base,
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+ const struct mbus_dram_target_info *dram)
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+{
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+ int i;
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+
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+ for (i = 0; i < USB3_MAX_WINDOWS; i++) {
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+ writel(0, base + USB3_WIN_CTRL(i));
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+ writel(0, base + USB3_WIN_BASE(i));
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+ }
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+
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+ for (i = 0; i < dram->num_cs; i++) {
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+ const struct mbus_dram_window *cs = dram->cs + i;
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+
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+ /* Write size, attributes and target id to control register */
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+ writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) |
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+ (dram->mbus_dram_target_id << 4) | 1,
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+ base + USB3_WIN_CTRL(i));
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+
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+ /* Write base address to base register */
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+ writel((cs->base & 0xffff0000), base + USB3_WIN_BASE(i));
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+ }
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+}
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+
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+int board_xhci_enable(fdt_addr_t base)
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+{
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+ const struct mbus_dram_target_info *dram;
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+
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+ printf("MVEBU XHCI INIT controller @ 0x%lx\n", base);
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+
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+ dram = mvebu_mbus_dram_info();
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+ xhci_mvebu_mbus_config((void __iomem *)base, dram);
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+
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+ return 0;
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+}
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+#endif
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+
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void enable_caches(void)
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{
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/* Avoid problem with e.g. neta ethernet driver */
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