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@@ -2,8 +2,9 @@
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/*
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* K3: ARM64 MMU setup
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*
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- * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
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+ * Copyright (C) 2018-2020 Texas Instruments Incorporated - https://www.ti.com/
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* Lokesh Vutla <lokeshvutla@ti.com>
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+ * Suman Anna <s-anna@ti.com>
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* (This file is derived from arch/arm/mach-zynqmp/cpu.c)
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*
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*/
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@@ -66,6 +67,8 @@ struct mm_region *mem_map = am654_mem_map;
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#endif /* CONFIG_SOC_K3_AM6 */
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#ifdef CONFIG_SOC_K3_J721E
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+
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+#ifdef CONFIG_TARGET_J721E_A72_EVM
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/* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */
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#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 6)
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@@ -122,4 +125,58 @@ struct mm_region j721e_mem_map[NR_MMU_REGIONS] = {
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};
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struct mm_region *mem_map = j721e_mem_map;
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+#endif /* CONFIG_TARGET_J721E_A72_EVM */
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+
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+#ifdef CONFIG_TARGET_J7200_A72_EVM
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+#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 5)
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+
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+/* ToDo: Add 64bit IO */
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+struct mm_region j7200_mem_map[NR_MMU_REGIONS] = {
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+ {
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+ .virt = 0x0UL,
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+ .phys = 0x0UL,
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+ .size = 0x80000000UL,
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+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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+ PTE_BLOCK_NON_SHARE |
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+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
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+ }, {
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+ .virt = 0x80000000UL,
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+ .phys = 0x80000000UL,
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+ .size = 0x20000000UL,
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+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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+ PTE_BLOCK_INNER_SHARE
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+ }, {
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+ .virt = 0xa0000000UL,
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+ .phys = 0xa0000000UL,
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+ .size = 0x04800000UL,
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+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
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+ PTE_BLOCK_NON_SHARE
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+ }, {
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+ .virt = 0xa4800000UL,
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+ .phys = 0xa4800000UL,
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+ .size = 0x5b800000UL,
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+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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+ PTE_BLOCK_INNER_SHARE
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+ }, {
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+ .virt = 0x880000000UL,
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+ .phys = 0x880000000UL,
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+ .size = 0x80000000UL,
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+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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+ PTE_BLOCK_INNER_SHARE
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+ }, {
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+ .virt = 0x500000000UL,
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+ .phys = 0x500000000UL,
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+ .size = 0x400000000UL,
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+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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+ PTE_BLOCK_NON_SHARE |
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+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
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+ }, {
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+ /* List terminator */
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+ 0,
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+ }
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+};
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+
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+struct mm_region *mem_map = j7200_mem_map;
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+#endif /* CONFIG_TARGET_J7200_A72_EVM */
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+
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#endif /* CONFIG_SOC_K3_J721E */
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