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@@ -945,6 +945,27 @@ void mx6sdl_dram_iocfg(unsigned width,
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mmdc1->entry = value; \
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} while (0)
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+/* see BOOT_CFG3 description Table 5-4. EIM Boot Fusemap */
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+#define BOOT_CFG3_DDR_MASK 0x30
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+#define BOOT_CFG3_EXT_DDR_MASK 0x33
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+
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+#define DDR_MMAP_NOC_SINGLE 0
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+#define DDR_MMAP_NOC_DUAL 0x31
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+
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+/* NoC ACTIVATE shifts */
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+#define NOC_RD_SHIFT 0
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+#define NOC_FAW_PERIOD_SHIFT 4
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+#define NOC_FAW_BANKS_SHIFT 10
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+
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+/* NoC DdrTiming shifts */
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+#define NOC_ACT_TO_ACT_SHIFT 0
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+#define NOC_RD_TO_MISS_SHIFT 6
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+#define NOC_WR_TO_MISS_SHIFT 12
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+#define NOC_BURST_LEN_SHIFT 18
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+#define NOC_RD_TO_WR_SHIFT 21
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+#define NOC_WR_TO_RD_SHIFT 26
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+#define NOC_BW_RATIO_SHIFT 31
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+
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/*
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* According JESD209-2B-LPDDR2: Table 103
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* WL: write latency
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@@ -1234,6 +1255,8 @@ void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo,
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{
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volatile struct mmdc_p_regs *mmdc0;
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volatile struct mmdc_p_regs *mmdc1;
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+ struct src *src_regs = (struct src *)SRC_BASE_ADDR;
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+ u8 soc_boot_cfg3 = (readl(&src_regs->sbmr1) >> 16) & 0xff;
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u32 val;
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u8 tcke, tcksrx, tcksre, txpdll, taofpd, taonpd, trrd;
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u8 todtlon, taxpd, tanpd, tcwl, txp, tfaw, tcl;
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@@ -1526,6 +1549,79 @@ void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo,
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/* Step 12: Configure and activate periodic refresh */
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mmdc0->mdref = (sysinfo->refsel << 14) | (sysinfo->refr << 11);
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+ /*
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+ * Step 13: i.MX6DQP only: If the NoC scheduler is enabled,
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+ * configure it and disable MMDC arbitration/reordering (see EB828)
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+ */
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+ if (is_mx6dqp() &&
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+ ((soc_boot_cfg3 & BOOT_CFG3_DDR_MASK) == DDR_MMAP_NOC_SINGLE ||
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+ (soc_boot_cfg3 & BOOT_CFG3_EXT_DDR_MASK) == DDR_MMAP_NOC_DUAL)) {
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+ struct mx6dqp_noc_sched_regs *noc_sched =
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+ (struct mx6dqp_noc_sched_regs *)MX6DQP_NOC_SCHED_BASE;
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+
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+ /*
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+ * These values are fixed based on integration parameters and
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+ * should not be modified
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+ */
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+ noc_sched->rlat = 0x00000040;
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+ noc_sched->ipu1 = 0x00000020;
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+ noc_sched->ipu2 = 0x00000020;
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+
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+ noc_sched->activate = (1 << NOC_FAW_BANKS_SHIFT) |
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+ (tfaw << NOC_FAW_PERIOD_SHIFT) |
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+ (trrd << NOC_RD_SHIFT);
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+ noc_sched->ddrtiming = (((sysinfo->dsize == 1) ? 1 : 0)
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+ << NOC_BW_RATIO_SHIFT) |
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+ ((tcwl + twtr) << NOC_WR_TO_RD_SHIFT) |
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+ ((tcl - tcwl + 2) << NOC_RD_TO_WR_SHIFT) |
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+ (4 << NOC_BURST_LEN_SHIFT) | /* BL8 */
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+ ((tcwl + twr + trp + trcd)
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+ << NOC_WR_TO_MISS_SHIFT) |
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+ ((trtp + trp + trcd - 4)
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+ << NOC_RD_TO_MISS_SHIFT) |
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+ (trc << NOC_ACT_TO_ACT_SHIFT);
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+
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+ if (sysinfo->dsize == 2) {
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+ if (ddr3_cfg->coladdr == 10) {
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+ if (ddr3_cfg->rowaddr == 15 &&
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+ sysinfo->ncs == 2)
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+ noc_sched->ddrconf = 4;
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+ else
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+ noc_sched->ddrconf = 0;
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+ } else if (ddr3_cfg->coladdr == 11) {
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+ noc_sched->ddrconf = 1;
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+ }
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+ } else {
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+ if (ddr3_cfg->coladdr == 9) {
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+ if (ddr3_cfg->rowaddr == 13)
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+ noc_sched->ddrconf = 2;
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+ else if (ddr3_cfg->rowaddr == 14)
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+ noc_sched->ddrconf = 15;
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+ } else if (ddr3_cfg->coladdr == 10) {
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+ if (ddr3_cfg->rowaddr == 14 &&
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+ sysinfo->ncs == 2)
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+ noc_sched->ddrconf = 14;
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+ else if (ddr3_cfg->rowaddr == 15 &&
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+ sysinfo->ncs == 2)
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+ noc_sched->ddrconf = 9;
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+ else
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+ noc_sched->ddrconf = 3;
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+ } else if (ddr3_cfg->coladdr == 11) {
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+ if (ddr3_cfg->rowaddr == 15 &&
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+ sysinfo->ncs == 2)
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+ noc_sched->ddrconf = 4;
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+ else
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+ noc_sched->ddrconf = 0;
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+ } else if (ddr3_cfg->coladdr == 12) {
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+ if (ddr3_cfg->rowaddr == 14)
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+ noc_sched->ddrconf = 1;
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+ }
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+ }
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+
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+ /* Disable MMDC arbitration/reordering */
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+ mmdc0->maarcr = 0x14420000;
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+ }
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+
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/* Step 13: Deassert config request - init complete */
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mmdc0->mdscr = 0x00000000;
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