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@@ -42,10 +42,14 @@
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#include <asm/io.h>
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#include <asm/processor.h>
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#include <asm/arch/cpu.h>
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+#include <wdt.h>
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+#include <dm.h>
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+#include <errno.h>
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/* Hardware timeout in seconds */
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#define WDT_HW_TIMEOUT 60
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+#if !CONFIG_IS_ENABLED(WDT)
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static unsigned int wdt_trgr_pattern = 0x1234;
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void hw_watchdog_reset(void)
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@@ -134,3 +138,113 @@ void hw_watchdog_init(void)
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while ((readl(&wdt->wdtwwps)) & WDT_WWPS_PEND_WSPR)
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;
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}
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+#else
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+static int omap3_wdt_reset(struct udevice *dev)
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+{
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+ struct omap3_wdt_priv *priv = dev_get_priv(dev);
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+
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+ priv->wdt_trgr_pattern = 0x1234;
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+/*
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+ * Somebody just triggered watchdog reset and write to WTGR register
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+ * is in progress. It is resetting right now, no need to trigger it
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+ * again
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+ */
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+ if ((readl(&priv->regs->wdtwwps)) & WDT_WWPS_PEND_WTGR)
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+ return 0;
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+
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+ priv->wdt_trgr_pattern = ~(priv->wdt_trgr_pattern);
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+ writel(priv->wdt_trgr_pattern, &priv->regs->wdtwtgr);
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+/*
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+ * Don't wait for posted write to complete, i.e. don't check
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+ * WDT_WWPS_PEND_WTGR bit in WWPS register. There is no writes to
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+ * WTGR register outside of this func, and if entering it
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+ * we see WDT_WWPS_PEND_WTGR bit set, it means watchdog reset
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+ * was just triggered. This prevents us from wasting time in busy
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+ * polling of WDT_WWPS_PEND_WTGR bit.
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+ */
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+ return 0;
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+}
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+
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+static int omap3_wdt_stop(struct udevice *dev)
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+{
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+ struct omap3_wdt_priv *priv = dev_get_priv(dev);
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+
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+/* disable watchdog */
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+ writel(0xAAAA, &priv->regs->wdtwspr);
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+ while (readl(&priv->regs->wdtwwps) != 0x0)
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+ ;
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+ writel(0x5555, &priv->regs->wdtwspr);
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+ while (readl(&priv->regs->wdtwwps) != 0x0)
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+ ;
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+ return 0;
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+}
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+
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+static int omap3_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags)
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+{
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+ struct omap3_wdt_priv *priv = dev_get_priv(dev);
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+ u32 pre_margin = GET_WLDR_VAL(timeout_ms);
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+/*
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+ * Make sure the watchdog is disabled. This is unfortunately required
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+ * because writing to various registers with the watchdog running has no
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+ * effect.
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+ */
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+ omap3_wdt_stop(dev);
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+
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+/* initialize prescaler */
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+ while (readl(&priv->regs->wdtwwps) & WDT_WWPS_PEND_WCLR)
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+ ;
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+
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+ writel(WDT_WCLR_PRE | (PTV << WDT_WCLR_PTV_OFF), &priv->regs->wdtwclr);
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+ while (readl(&priv->regs->wdtwwps) & WDT_WWPS_PEND_WCLR)
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+ ;
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+/* just count up at 32 KHz */
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+ while (readl(&priv->regs->wdtwwps) & WDT_WWPS_PEND_WLDR)
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+ ;
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+
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+ writel(pre_margin, &priv->regs->wdtwldr);
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+ while (readl(&priv->regs->wdtwwps) & WDT_WWPS_PEND_WLDR)
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+ ;
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+/* Sequence to enable the watchdog */
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+ writel(0xBBBB, &priv->regs->wdtwspr);
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+ while ((readl(&priv->regs->wdtwwps)) & WDT_WWPS_PEND_WSPR)
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+ ;
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+
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+ writel(0x4444, &priv->regs->wdtwspr);
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+ while ((readl(&priv->regs->wdtwwps)) & WDT_WWPS_PEND_WSPR)
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+ ;
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+
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+ return 0;
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+}
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+
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+static int omap3_wdt_probe(struct udevice *dev)
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+{
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+ struct omap3_wdt_priv *priv = dev_get_priv(dev);
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+
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+ priv->regs = (struct wd_timer *)devfdt_get_addr(dev);
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+ if (!priv->regs)
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+ return -EINVAL;
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+
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+ debug("%s: Probing wdt%u\n", __func__, dev->seq);
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+ return 0;
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+}
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+
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+static const struct wdt_ops omap3_wdt_ops = {
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+ .start = omap3_wdt_start,
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+ .stop = omap3_wdt_stop,
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+ .reset = omap3_wdt_reset,
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+};
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+
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+static const struct udevice_id omap3_wdt_ids[] = {
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+ { .compatible = "ti,omap3-wdt" },
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+ { }
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+};
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+
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+U_BOOT_DRIVER(omap3_wdt) = {
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+ .name = "omap3_wdt",
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+ .id = UCLASS_WDT,
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+ .of_match = omap3_wdt_ids,
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+ .ops = &omap3_wdt_ops,
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+ .probe = omap3_wdt_probe,
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+ .priv_auto_alloc_size = sizeof(struct omap3_wdt_priv),
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+};
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+#endif /* !CONFIG_IS_ENABLED(WDT) */
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