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@@ -145,13 +145,11 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg
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#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
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#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
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-#define CONFIG_PCI_INDIRECT_BRIDGE
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#define CONFIG_PCIE1 /* PCIE controller 1 */
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#define CONFIG_PCIE2 /* PCIE controller 2 */
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#define CONFIG_PCIE3 /* PCIE controller 3 */
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#define CONFIG_PCIE4 /* PCIE controller 4 */
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-#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
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#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
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#define CONFIG_ENV_OVERWRITE
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@@ -524,51 +522,55 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg
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/* controller 1, direct to uli, tgtid 3, Base address 20000 */
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#ifdef CONFIG_PCIE1
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#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
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-#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
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#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
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-#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
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#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
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-#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
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#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
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-#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
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#endif
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/* controller 2, Slot 2, tgtid 2, Base address 201000 */
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#ifdef CONFIG_PCIE2
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#define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
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-#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
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#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
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-#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
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#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
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-#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
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#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
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-#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
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#endif
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/* controller 3, Slot 1, tgtid 1, Base address 202000 */
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#ifdef CONFIG_PCIE3
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#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
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-#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
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#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
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-#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
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#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
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-#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
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#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
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-#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
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#endif
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/* controller 4, Base address 203000 */
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#ifdef CONFIG_PCIE4
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#define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000
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-#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
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#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull
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-#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
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#define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000
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-#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
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#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
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-#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
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#endif
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+#if !defined(CONFIG_DM_PCI)
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+#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
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+#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
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+#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
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+#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
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+#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
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+#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
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+#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
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+#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
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+#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
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+#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
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+#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
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+#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
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+#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
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+#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
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+#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
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+#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
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+#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
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+#define CONFIG_PCI_INDIRECT_BRIDGE
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+#endif
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#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
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#endif /* CONFIG_PCI */
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