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@@ -0,0 +1,172 @@
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+// SPDX-License-Identifier: GPL-2.0+
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+/*
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+ * Copyright (C) 2020 SiFive, Inc
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+ * For SiFive's PWM IP block documentation please refer Chapter 14 of
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+ * Reference Manual : https://static.dev.sifive.com/FU540-C000-v1.0.pdf
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+ *
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+ * Limitations:
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+ * - When changing both duty cycle and period, we cannot prevent in
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+ * software that the output might produce a period with mixed
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+ * settings (new period length and old duty cycle).
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+ * - The hardware cannot generate a 100% duty cycle.
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+ * - The hardware generates only inverted output.
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+ */
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+
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+#include <common.h>
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+#include <clk.h>
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+#include <div64.h>
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+#include <dm.h>
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+#include <pwm.h>
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+#include <regmap.h>
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+#include <linux/io.h>
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+#include <linux/log2.h>
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+#include <linux/bitfield.h>
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+
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+/* PWMCFG fields */
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+#define PWM_SIFIVE_PWMCFG_SCALE GENMASK(3, 0)
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+#define PWM_SIFIVE_PWMCFG_STICKY BIT(8)
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+#define PWM_SIFIVE_PWMCFG_ZERO_CMP BIT(9)
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+#define PWM_SIFIVE_PWMCFG_DEGLITCH BIT(10)
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+#define PWM_SIFIVE_PWMCFG_EN_ALWAYS BIT(12)
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+#define PWM_SIFIVE_PWMCFG_EN_ONCE BIT(13)
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+#define PWM_SIFIVE_PWMCFG_CENTER BIT(16)
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+#define PWM_SIFIVE_PWMCFG_GANG BIT(24)
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+#define PWM_SIFIVE_PWMCFG_IP BIT(28)
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+
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+/* PWM_SIFIVE_SIZE_PWMCMP is used to calculate offset for pwmcmpX registers */
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+#define PWM_SIFIVE_SIZE_PWMCMP 4
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+#define PWM_SIFIVE_CMPWIDTH 16
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+
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+DECLARE_GLOBAL_DATA_PTR;
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+
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+struct pwm_sifive_regs {
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+ unsigned long cfg;
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+ unsigned long cnt;
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+ unsigned long pwms;
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+ unsigned long cmp0;
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+};
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+
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+struct pwm_sifive_data {
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+ struct pwm_sifive_regs regs;
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+};
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+
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+struct pwm_sifive_priv {
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+ void __iomem *base;
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+ ulong freq;
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+ const struct pwm_sifive_data *data;
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+};
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+
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+static int pwm_sifive_set_config(struct udevice *dev, uint channel,
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+ uint period_ns, uint duty_ns)
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+{
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+ struct pwm_sifive_priv *priv = dev_get_priv(dev);
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+ const struct pwm_sifive_regs *regs = &priv->data->regs;
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+ unsigned long scale_pow;
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+ unsigned long long num;
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+ u32 scale, val = 0, frac;
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+
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+ debug("%s: period_ns=%u, duty_ns=%u\n", __func__, period_ns, duty_ns);
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+
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+ /*
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+ * The PWM unit is used with pwmzerocmp=0, so the only way to modify the
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+ * period length is using pwmscale which provides the number of bits the
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+ * counter is shifted before being feed to the comparators. A period
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+ * lasts (1 << (PWM_SIFIVE_CMPWIDTH + pwmscale)) clock ticks.
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+ * (1 << (PWM_SIFIVE_CMPWIDTH + scale)) * 10^9/rate = period
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+ */
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+ scale_pow = lldiv((uint64_t)priv->freq * period_ns, 1000000000);
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+ scale = clamp(ilog2(scale_pow) - PWM_SIFIVE_CMPWIDTH, 0, 0xf);
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+ val |= FIELD_PREP(PWM_SIFIVE_PWMCFG_SCALE, scale);
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+
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+ /*
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+ * The problem of output producing mixed setting as mentioned at top,
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+ * occurs here. To minimize the window for this problem, we are
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+ * calculating the register values first and then writing them
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+ * consecutively
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+ */
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+ num = (u64)duty_ns * (1U << PWM_SIFIVE_CMPWIDTH);
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+ frac = DIV_ROUND_CLOSEST_ULL(num, period_ns);
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+ frac = min(frac, (1U << PWM_SIFIVE_CMPWIDTH) - 1);
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+
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+ writel(val, priv->base + regs->cfg);
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+ writel(frac, priv->base + regs->cmp0 + channel *
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+ PWM_SIFIVE_SIZE_PWMCMP);
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+
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+ return 0;
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+}
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+
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+static int pwm_sifive_set_enable(struct udevice *dev, uint channel, bool enable)
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+{
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+ struct pwm_sifive_priv *priv = dev_get_priv(dev);
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+ const struct pwm_sifive_regs *regs = &priv->data->regs;
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+ u32 val;
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+
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+ debug("%s: Enable '%s'\n", __func__, dev->name);
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+
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+ if (enable) {
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+ val = readl(priv->base + regs->cfg);
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+ val |= PWM_SIFIVE_PWMCFG_EN_ALWAYS;
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+ writel(val, priv->base + regs->cfg);
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+ } else {
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+ writel(0, priv->base + regs->cmp0 + channel *
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+ PWM_SIFIVE_SIZE_PWMCMP);
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+ }
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+
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+ return 0;
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+}
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+
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+static int pwm_sifive_ofdata_to_platdata(struct udevice *dev)
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+{
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+ struct pwm_sifive_priv *priv = dev_get_priv(dev);
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+
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+ priv->base = dev_read_addr_ptr(dev);
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+
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+ return 0;
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+}
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+
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+static int pwm_sifive_probe(struct udevice *dev)
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+{
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+ struct pwm_sifive_priv *priv = dev_get_priv(dev);
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+ struct clk clk;
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+ int ret = 0;
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+
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+ ret = clk_get_by_index(dev, 0, &clk);
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+ if (ret < 0) {
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+ debug("%s get clock fail!\n", __func__);
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+ return -EINVAL;
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+ }
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+
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+ priv->freq = clk_get_rate(&clk);
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+ priv->data = (struct pwm_sifive_data *)dev_get_driver_data(dev);
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+
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+ return 0;
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+}
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+
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+static const struct pwm_ops pwm_sifive_ops = {
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+ .set_config = pwm_sifive_set_config,
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+ .set_enable = pwm_sifive_set_enable,
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+};
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+
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+static const struct pwm_sifive_data pwm_data = {
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+ .regs = {
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+ .cfg = 0x00,
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+ .cnt = 0x08,
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+ .pwms = 0x10,
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+ .cmp0 = 0x20,
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+ },
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+};
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+
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+static const struct udevice_id pwm_sifive_ids[] = {
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+ { .compatible = "sifive,pwm0", .data = (ulong)&pwm_data},
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+ { }
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+};
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+
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+U_BOOT_DRIVER(pwm_sifive) = {
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+ .name = "pwm_sifive",
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+ .id = UCLASS_PWM,
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+ .of_match = pwm_sifive_ids,
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+ .ops = &pwm_sifive_ops,
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+ .ofdata_to_platdata = pwm_sifive_ofdata_to_platdata,
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+ .probe = pwm_sifive_probe,
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+ .priv_auto_alloc_size = sizeof(struct pwm_sifive_priv),
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+};
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