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@@ -37,7 +37,7 @@ DECLARE_GLOBAL_DATA_PTR;
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static char *cpu_warning = "\n " \
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"*** Warning: CPU Core has Silicon Bugs -- Check the Errata ***";
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-static int check_CPU (long clock, uint pvr, uint immr)
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+static int check_CPU(long clock, uint pvr, uint immr)
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{
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char *id_str =
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NULL;
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@@ -73,22 +73,25 @@ static int check_CPU (long clock, uint pvr, uint immr)
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id_str =
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"PC866x"; /* Unknown chip from MPC866 family */
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break;
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- case 0x09000000: pre = 'M'; mid = suf = ""; m = 1;
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+ case 0x09000000:
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+ pre = 'M'; mid = suf = ""; m = 1;
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if (id_str == NULL)
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id_str = "PC885"; /* 870/875/880/885 */
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break;
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- default: suf = NULL; break;
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+ default:
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+ suf = NULL;
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+ break;
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}
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if (id_str == NULL)
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id_str = "PC86x"; /* Unknown 86x chip */
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if (suf)
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- printf ("%c%s%sZPnn%s", pre, id_str, mid, suf);
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+ printf("%c%s%sZPnn%s", pre, id_str, mid, suf);
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else
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- printf ("unknown M%s (0x%08x)", id_str, k);
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+ printf("unknown M%s (0x%08x)", id_str, k);
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- printf (" at %s MHz: ", strmhz (buf, clock));
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+ printf(" at %s MHz: ", strmhz(buf, clock));
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print_size(checkicache(), " I-Cache ");
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print_size(checkdcache(), " D-Cache");
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@@ -97,64 +100,63 @@ static int check_CPU (long clock, uint pvr, uint immr)
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out_be32(&immap->im_cpm.cp_fec.fec_addr_low, 0x12345678);
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if (in_be32(&immap->im_cpm.cp_fec.fec_addr_low) == 0x12345678)
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- printf (" FEC present");
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+ printf(" FEC present");
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- if (!m) {
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- puts (cpu_warning);
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- }
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+ if (!m)
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+ puts(cpu_warning);
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- putc ('\n');
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+ putc('\n');
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return 0;
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}
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/* ------------------------------------------------------------------------- */
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-int checkcpu (void)
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+int checkcpu(void)
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{
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ulong clock = gd->cpu_clk;
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- uint immr = get_immr (0); /* Return full IMMR contents */
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- uint pvr = get_pvr ();
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+ uint immr = get_immr(0); /* Return full IMMR contents */
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+ uint pvr = get_pvr();
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- puts ("CPU: ");
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+ puts("CPU: ");
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- return check_CPU (clock, pvr, immr);
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+ return check_CPU(clock, pvr, immr);
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}
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/* ------------------------------------------------------------------------- */
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/* L1 i-cache */
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-int checkicache (void)
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+int checkicache(void)
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{
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immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
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memctl8xx_t __iomem *memctl = &immap->im_memctl;
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- u32 cacheon = rd_ic_cst () & IDC_ENABLED;
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+ u32 cacheon = rd_ic_cst() & IDC_ENABLED;
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/* probe in flash memoryarea */
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u32 k = in_be32(&memctl->memc_br0) & ~0x00007fff;
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u32 m;
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u32 lines = -1;
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- wr_ic_cst (IDC_UNALL);
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- wr_ic_cst (IDC_INVALL);
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- wr_ic_cst (IDC_DISABLE);
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+ wr_ic_cst(IDC_UNALL);
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+ wr_ic_cst(IDC_INVALL);
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+ wr_ic_cst(IDC_DISABLE);
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__asm__ volatile ("isync");
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- while (!((m = rd_ic_cst ()) & IDC_CERR2)) {
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- wr_ic_adr (k);
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- wr_ic_cst (IDC_LDLCK);
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+ while (!((m = rd_ic_cst()) & IDC_CERR2)) {
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+ wr_ic_adr(k);
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+ wr_ic_cst(IDC_LDLCK);
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__asm__ volatile ("isync");
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lines++;
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- k += 0x10; /* the number of bytes in a cacheline */
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+ k += 0x10; /* the number of bytes in a cacheline */
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}
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- wr_ic_cst (IDC_UNALL);
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- wr_ic_cst (IDC_INVALL);
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+ wr_ic_cst(IDC_UNALL);
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+ wr_ic_cst(IDC_INVALL);
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if (cacheon)
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- wr_ic_cst (IDC_ENABLE);
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+ wr_ic_cst(IDC_ENABLE);
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else
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- wr_ic_cst (IDC_DISABLE);
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+ wr_ic_cst(IDC_DISABLE);
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__asm__ volatile ("isync");
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@@ -165,41 +167,41 @@ int checkicache (void)
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/* L1 d-cache */
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/* call with cache disabled */
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-int checkdcache (void)
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+int checkdcache(void)
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{
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immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
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memctl8xx_t __iomem *memctl = &immap->im_memctl;
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- u32 cacheon = rd_dc_cst () & IDC_ENABLED;
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+ u32 cacheon = rd_dc_cst() & IDC_ENABLED;
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/* probe in flash memoryarea */
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u32 k = in_be32(&memctl->memc_br0) & ~0x00007fff;
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u32 m;
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u32 lines = -1;
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- wr_dc_cst (IDC_UNALL);
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- wr_dc_cst (IDC_INVALL);
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- wr_dc_cst (IDC_DISABLE);
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+ wr_dc_cst(IDC_UNALL);
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+ wr_dc_cst(IDC_INVALL);
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+ wr_dc_cst(IDC_DISABLE);
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- while (!((m = rd_dc_cst ()) & IDC_CERR2)) {
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- wr_dc_adr (k);
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- wr_dc_cst (IDC_LDLCK);
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+ while (!((m = rd_dc_cst()) & IDC_CERR2)) {
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+ wr_dc_adr(k);
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+ wr_dc_cst(IDC_LDLCK);
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lines++;
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k += 0x10; /* the number of bytes in a cacheline */
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}
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- wr_dc_cst (IDC_UNALL);
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- wr_dc_cst (IDC_INVALL);
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+ wr_dc_cst(IDC_UNALL);
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+ wr_dc_cst(IDC_INVALL);
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if (cacheon)
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- wr_dc_cst (IDC_ENABLE);
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+ wr_dc_cst(IDC_ENABLE);
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else
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- wr_dc_cst (IDC_DISABLE);
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+ wr_dc_cst(IDC_DISABLE);
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return lines << 4;
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};
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/* ------------------------------------------------------------------------- */
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-void upmconfig (uint upm, uint * table, uint size)
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+void upmconfig(uint upm, uint *table, uint size)
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{
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uint i;
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uint addr = 0;
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@@ -215,7 +217,7 @@ void upmconfig (uint upm, uint * table, uint size)
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/* ------------------------------------------------------------------------- */
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-int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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ulong msr, addr;
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@@ -226,10 +228,10 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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/* Interrupts and MMU off */
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__asm__ volatile ("mtspr 81, 0");
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- __asm__ volatile ("mfmsr %0":"=r" (msr));
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+ __asm__ volatile ("mfmsr %0" : "=r" (msr));
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msr &= ~0x1030;
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- __asm__ volatile ("mtmsr %0"::"r" (msr));
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+ __asm__ volatile ("mtmsr %0" : : "r" (msr));
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/*
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* Trying to execute the next instruction at a non-existing address
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@@ -239,14 +241,15 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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addr = CONFIG_SYS_RESET_ADDRESS;
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#else
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/*
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- * note: when CONFIG_SYS_MONITOR_BASE points to a RAM address, CONFIG_SYS_MONITOR_BASE
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- * - sizeof (ulong) is usually a valid address. Better pick an address
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- * known to be invalid on your system and assign it to CONFIG_SYS_RESET_ADDRESS.
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+ * note: when CONFIG_SYS_MONITOR_BASE points to a RAM address,
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+ * CONFIG_SYS_MONITOR_BASE - sizeof (ulong) is usually a valid address.
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+ * Better pick an address known to be invalid on your system and assign
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+ * it to CONFIG_SYS_RESET_ADDRESS.
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* "(ulong)-1" used to be a good choice for many systems...
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*/
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- addr = CONFIG_SYS_MONITOR_BASE - sizeof (ulong);
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+ addr = CONFIG_SYS_MONITOR_BASE - sizeof(ulong);
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#endif
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- ((void (*)(void)) addr) ();
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+ ((void (*)(void)) addr)();
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return 1;
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}
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@@ -257,14 +260,14 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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*
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* See sections 14.2 and 14.6 of the User's Manual
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*/
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-unsigned long get_tbclk (void)
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+unsigned long get_tbclk(void)
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{
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- uint immr = get_immr (0); /* Return full IMMR contents */
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+ uint immr = get_immr(0); /* Return full IMMR contents */
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immap_t __iomem *immap = (immap_t __iomem *)(immr & 0xFFFF0000);
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ulong oscclk, factor, pll;
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if (in_be32(&immap->im_clkrst.car_sccr) & SCCR_TBS)
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- return (gd->cpu_clk / 16);
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+ return gd->cpu_clk / 16;
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pll = in_be32(&immap->im_clkrst.car_plprcr);
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@@ -281,28 +284,28 @@ unsigned long get_tbclk (void)
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* (PDF + 1) * 2^S
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*
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*/
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- factor = (PLPRCR_val(MFI) + PLPRCR_val(MFN)/(PLPRCR_val(MFD)+1))/
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- (PLPRCR_val(PDF)+1) / (1<<PLPRCR_val(S));
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+ factor = (PLPRCR_val(MFI) + PLPRCR_val(MFN) / (PLPRCR_val(MFD) + 1)) /
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+ (PLPRCR_val(PDF) + 1) / (1 << PLPRCR_val(S));
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oscclk = gd->cpu_clk / factor;
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if ((in_be32(&immap->im_clkrst.car_sccr) & SCCR_RTSEL) == 0 ||
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factor > 2)
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- return (oscclk / 4);
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+ return oscclk / 4;
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- return (oscclk / 16);
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+ return oscclk / 16;
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}
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/* ------------------------------------------------------------------------- */
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#if defined(CONFIG_WATCHDOG)
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-void watchdog_reset (void)
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+void watchdog_reset(void)
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{
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- int re_enable = disable_interrupts ();
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+ int re_enable = disable_interrupts();
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reset_8xx_watchdog((immap_t __iomem *)CONFIG_SYS_IMMR);
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if (re_enable)
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- enable_interrupts ();
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+ enable_interrupts();
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}
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#endif /* CONFIG_WATCHDOG */
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