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@@ -12,7 +12,6 @@
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#include <asm/arch/at91sam9g45_matrix.h>
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#include <asm/arch/at91sam9_smc.h>
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#include <asm/arch/at91_common.h>
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-#include <asm/arch/at91_pmc.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/clk.h>
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#include <lcd.h>
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@@ -36,7 +35,6 @@ void at91sam9m10g45ek_nand_hw_init(void)
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{
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struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
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struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
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- struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
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unsigned long csa;
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/* Enable CS3 */
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@@ -63,7 +61,7 @@ void at91sam9m10g45ek_nand_hw_init(void)
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AT91_SMC_MODE_TDF_CYCLE(3),
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&smc->cs[3].mode);
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- writel(1 << ATMEL_ID_PIOC, &pmc->pcer);
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+ at91_periph_clk_enable(ATMEL_ID_PIOC);
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/* Configure RDY/BSY */
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at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
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@@ -130,13 +128,11 @@ static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
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void mem_init(void)
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{
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- struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
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struct atmel_mpddrc_config ddr2;
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ddr2_conf(&ddr2);
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- /* enable DDR2 clock */
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- writel(AT91_PMC_DDR, &pmc->scer);
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+ at91_system_clk_enable(AT91_PMC_DDR);
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/* DDRAM2 Controller initialize */
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ddr2_init(ATMEL_BASE_DDRSDRC0, ATMEL_BASE_CS6, &ddr2);
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@@ -146,9 +142,7 @@ void mem_init(void)
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#ifdef CONFIG_CMD_USB
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static void at91sam9m10g45ek_usb_hw_init(void)
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{
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- struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
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-
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- writel(1 << ATMEL_ID_PIODE, &pmc->pcer);
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+ at91_periph_clk_enable(ATMEL_ID_PIODE);
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at91_set_gpio_output(AT91_PIN_PD1, 0);
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at91_set_gpio_output(AT91_PIN_PD3, 0);
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@@ -158,11 +152,9 @@ static void at91sam9m10g45ek_usb_hw_init(void)
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#ifdef CONFIG_MACB
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static void at91sam9m10g45ek_macb_hw_init(void)
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{
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- struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
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struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
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- /* Enable clock */
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- writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
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+ at91_periph_clk_enable(ATMEL_ID_EMAC);
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/*
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* Disable pull-up on:
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@@ -222,8 +214,6 @@ void lcd_disable(void)
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static void at91sam9m10g45ek_lcd_hw_init(void)
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{
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- struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
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-
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at91_set_A_periph(AT91_PIN_PE0, 0); /* LCDDPWR */
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at91_set_A_periph(AT91_PIN_PE2, 0); /* LCDCC */
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at91_set_A_periph(AT91_PIN_PE3, 0); /* LCDVSYNC */
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@@ -255,7 +245,7 @@ static void at91sam9m10g45ek_lcd_hw_init(void)
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at91_set_A_periph(AT91_PIN_PE29, 0); /* LCDD22 */
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at91_set_A_periph(AT91_PIN_PE30, 0); /* LCDD23 */
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- writel(1 << ATMEL_ID_LCDC, &pmc->pcer);
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+ at91_periph_clk_enable(ATMEL_ID_LCDC);
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gd->fb_base = CONFIG_AT91SAM9G45_LCD_BASE;
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}
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