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@@ -1379,7 +1379,7 @@ static int tfa_dram_init_banksize(void)
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if (i > 0)
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ret = 0;
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-#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
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+#if defined(CONFIG_RESV_RAM) && !defined(CONFIG_SPL_BUILD)
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/* Assign memory for MC */
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#ifdef CONFIG_SYS_DDR_BLOCK3_BASE
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if (gd->bd->bi_dram[2].size >=
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@@ -1402,7 +1402,7 @@ static int tfa_dram_init_banksize(void)
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board_reserve_ram_top(gd->bd->bi_dram[0].size);
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}
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}
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-#endif /* CONFIG_FSL_MC_ENET */
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+#endif /* CONFIG_RESV_RAM */
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return ret;
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}
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@@ -1465,7 +1465,7 @@ int dram_init_banksize(void)
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}
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#endif /* CONFIG_SYS_MEM_RESERVE_SECURE */
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-#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
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+#if defined(CONFIG_RESV_RAM) && !defined(CONFIG_SPL_BUILD)
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/* Assign memory for MC */
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#ifdef CONFIG_SYS_DDR_BLOCK3_BASE
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if (gd->bd->bi_dram[2].size >=
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@@ -1488,7 +1488,7 @@ int dram_init_banksize(void)
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board_reserve_ram_top(gd->bd->bi_dram[0].size);
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}
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}
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-#endif /* CONFIG_FSL_MC_ENET */
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+#endif /* CONFIG_RESV_RAM */
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#ifdef CONFIG_SYS_DP_DDR_BASE_PHY
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#ifdef CONFIG_SYS_DDR_BLOCK3_BASE
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