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@@ -100,9 +100,20 @@
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#define SPI_PUP_EN BIT(5)
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#define MVEBU_CORE_DIV_CLK_CTRL(i) (MVEBU_CLOCK_BASE + ((i) * 0x8))
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+#ifdef CONFIG_ARMADA_MSYS
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+#define MVEBU_DFX_DIV_CLK_CTRL(i) (MVEBU_DFX_BASE + 0xf8000 + 0x250 + ((i) * 0x4))
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+#define NAND_ECC_DIVCKL_RATIO_OFFS 6
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+#define NAND_ECC_DIVCKL_RATIO_MASK (0xF << NAND_ECC_DIVCKL_RATIO_OFFS)
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+#else
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#define MVEBU_DFX_DIV_CLK_CTRL(i) (MVEBU_DFX_BASE + 0x250 + ((i) * 0x4))
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+#endif
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+#ifdef CONFIG_ARMADA_MSYS
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+#define NAND_ECC_DIVCKL_RATIO_OFFS 6
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+#define NAND_ECC_DIVCKL_RATIO_MASK (0xF << NAND_ECC_DIVCKL_RATIO_OFFS)
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+#else
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#define NAND_ECC_DIVCKL_RATIO_OFFS 8
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#define NAND_ECC_DIVCKL_RATIO_MASK (0x3F << NAND_ECC_DIVCKL_RATIO_OFFS)
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+#endif
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#define SDRAM_MAX_CS 4
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#define SDRAM_ADDR_MASK 0xFF000000
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