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@@ -43,6 +43,7 @@
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*/
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#include <dt-bindings/clock/sun50i-a64-ccu.h>
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+#include <dt-bindings/clock/sun8i-r-ccu.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/reset/sun50i-a64-ccu.h>
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@@ -51,6 +52,26 @@
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#address-cells = <1>;
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#size-cells = <1>;
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+ chosen {
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ ranges;
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+
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+/*
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+ * The pipeline mixer0-lcd0 depends on clock CLK_MIXER0 from DE2 CCU.
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+ * However there is no support for this clock on A64 yet, so we depend
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+ * on the upstream clocks here to keep them (and thus CLK_MIXER0) up.
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+ */
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+ simplefb_lcd: framebuffer-lcd {
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+ compatible = "allwinner,simple-framebuffer",
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+ "simple-framebuffer";
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+ allwinner,pipeline = "mixer0-lcd0";
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+ clocks = <&ccu CLK_TCON0>,
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+ <&ccu CLK_DE>, <&ccu CLK_BUS_DE>;
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+ status = "disabled";
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+ };
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+ };
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+
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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@@ -111,6 +132,24 @@
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method = "smc";
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};
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+ sound_spdif {
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+ compatible = "simple-audio-card";
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+ simple-audio-card,name = "On-board SPDIF";
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+
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+ simple-audio-card,cpu {
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+ sound-dai = <&spdif>;
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+ };
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+
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+ simple-audio-card,codec {
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+ sound-dai = <&spdif_out>;
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+ };
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+ };
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+
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+ spdif_out: spdif-out {
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+ #sound-dai-cells = <0>;
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+ compatible = "linux,spdif-dit";
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+ };
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+
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13
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@@ -129,6 +168,23 @@
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#size-cells = <1>;
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ranges;
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+ syscon: syscon@1c00000 {
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+ compatible = "allwinner,sun50i-a64-system-controller",
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+ "syscon";
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+ reg = <0x01c00000 0x1000>;
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+ };
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+
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+ dma: dma-controller@1c02000 {
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+ compatible = "allwinner,sun50i-a64-dma";
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+ reg = <0x01c02000 0x1000>;
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+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&ccu CLK_BUS_DMA>;
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+ dma-channels = <8>;
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+ dma-requests = <27>;
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+ resets = <&ccu RST_BUS_DMA>;
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+ #dma-cells = <1>;
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+ };
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+
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mmc0: mmc@1c0f000 {
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compatible = "allwinner,sun50i-a64-mmc";
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reg = <0x01c0f000 0x1000>;
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@@ -171,7 +227,7 @@
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#size-cells = <0>;
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};
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- usb_otg: usb@01c19000 {
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+ usb_otg: usb@1c19000 {
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compatible = "allwinner,sun8i-a33-musb";
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reg = <0x01c19000 0x0400>;
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clocks = <&ccu CLK_BUS_OTG>;
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@@ -184,7 +240,7 @@
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status = "disabled";
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};
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- usbphy: phy@01c19400 {
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+ usbphy: phy@1c19400 {
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compatible = "allwinner,sun50i-a64-usb-phy";
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reg = <0x01c19400 0x14>,
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<0x01c1a800 0x4>,
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@@ -204,7 +260,7 @@
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#phy-cells = <1>;
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};
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- ehci0: usb@01c1a000 {
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+ ehci0: usb@1c1a000 {
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compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
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reg = <0x01c1a000 0x100>;
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interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
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@@ -216,7 +272,7 @@
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status = "disabled";
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};
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- ohci0: usb@01c1a400 {
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+ ohci0: usb@1c1a400 {
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compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
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reg = <0x01c1a400 0x100>;
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interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
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@@ -226,7 +282,7 @@
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status = "disabled";
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};
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- ehci1: usb@01c1b000 {
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+ ehci1: usb@1c1b000 {
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compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
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reg = <0x01c1b000 0x100>;
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interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
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@@ -240,7 +296,7 @@
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status = "disabled";
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};
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- ohci1: usb@01c1b400 {
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+ ohci1: usb@1c1b400 {
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compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
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reg = <0x01c1b400 0x100>;
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interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
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@@ -252,7 +308,7 @@
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status = "disabled";
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};
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- ccu: clock@01c20000 {
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+ ccu: clock@1c20000 {
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compatible = "allwinner,sun50i-a64-ccu";
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reg = <0x01c20000 0x400>;
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clocks = <&osc24M>, <&osc32k>;
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@@ -273,6 +329,11 @@
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interrupt-controller;
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#interrupt-cells = <3>;
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+ i2c0_pins: i2c0_pins {
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+ pins = "PH0", "PH1";
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+ function = "i2c0";
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+ };
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+
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i2c1_pins: i2c1_pins {
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pins = "PH2", "PH3";
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function = "i2c1";
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@@ -303,7 +364,37 @@
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bias-pull-up;
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};
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- uart0_pins_a: uart0@0 {
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+ rmii_pins: rmii_pins {
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+ pins = "PD10", "PD11", "PD13", "PD14", "PD17",
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+ "PD18", "PD19", "PD20", "PD22", "PD23";
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+ function = "emac";
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+ drive-strength = <40>;
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+ };
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+
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+ rgmii_pins: rgmii_pins {
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+ pins = "PD8", "PD9", "PD10", "PD11", "PD12",
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+ "PD13", "PD15", "PD16", "PD17", "PD18",
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+ "PD19", "PD20", "PD21", "PD22", "PD23";
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+ function = "emac";
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+ drive-strength = <40>;
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+ };
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+
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+ spdif_tx_pin: spdif {
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+ pins = "PH8";
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+ function = "spdif";
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+ };
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+
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+ spi0_pins: spi0 {
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+ pins = "PC0", "PC1", "PC2", "PC3";
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+ function = "spi0";
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+ };
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+
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+ spi1_pins: spi1 {
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+ pins = "PD0", "PD1", "PD2", "PD3";
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+ function = "spi1";
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+ };
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+
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+ uart0_pins_a: uart0 {
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pins = "PB8", "PB9";
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function = "uart0";
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};
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@@ -317,9 +408,73 @@
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pins = "PG8", "PG9";
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function = "uart1";
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};
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+
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+ uart2_pins: uart2-pins {
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+ pins = "PB0", "PB1";
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+ function = "uart2";
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+ };
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+
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+ uart3_pins: uart3-pins {
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+ pins = "PD0", "PD1";
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+ function = "uart3";
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+ };
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+
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+ uart4_pins: uart4-pins {
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+ pins = "PD2", "PD3";
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+ function = "uart4";
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+ };
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+
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+ uart4_rts_cts_pins: uart4-rts-cts-pins {
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+ pins = "PD4", "PD5";
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+ function = "uart4";
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+ };
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+ };
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+
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+ spdif: spdif@1c21000 {
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+ #sound-dai-cells = <0>;
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+ compatible = "allwinner,sun50i-a64-spdif",
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+ "allwinner,sun8i-h3-spdif";
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+ reg = <0x01c21000 0x400>;
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+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
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+ resets = <&ccu RST_BUS_SPDIF>;
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+ clock-names = "apb", "spdif";
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+ dmas = <&dma 2>;
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+ dma-names = "tx";
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&spdif_tx_pin>;
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+ status = "disabled";
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+ };
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+
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+ i2s0: i2s@1c22000 {
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+ #sound-dai-cells = <0>;
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+ compatible = "allwinner,sun50i-a64-i2s",
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+ "allwinner,sun8i-h3-i2s";
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+ reg = <0x01c22000 0x400>;
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+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>;
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+ clock-names = "apb", "mod";
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+ resets = <&ccu RST_BUS_I2S0>;
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+ dma-names = "rx", "tx";
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+ dmas = <&dma 3>, <&dma 3>;
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+ status = "disabled";
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+ };
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+
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+ i2s1: i2s@1c22400 {
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+ #sound-dai-cells = <0>;
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+ compatible = "allwinner,sun50i-a64-i2s",
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+ "allwinner,sun8i-h3-i2s";
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+ reg = <0x01c22400 0x400>;
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+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>;
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+ clock-names = "apb", "mod";
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+ resets = <&ccu RST_BUS_I2S1>;
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+ dma-names = "rx", "tx";
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+ dmas = <&dma 4>, <&dma 4>;
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+ status = "disabled";
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};
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- pwm: pwm@01c21400 {
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+ pwm: pwm@1c21400 {
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compatible = "allwinner,sun50i-a64-pwm",
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"allwinner,sun5i-a13-pwm";
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reg = <0x01c21400 0x8>;
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@@ -334,8 +489,8 @@
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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- clocks = <&ccu 67>;
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- resets = <&ccu 46>;
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+ clocks = <&ccu CLK_BUS_UART0>;
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+ resets = <&ccu RST_BUS_UART0>;
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status = "disabled";
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};
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@@ -345,8 +500,8 @@
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interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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- clocks = <&ccu 68>;
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- resets = <&ccu 47>;
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+ clocks = <&ccu CLK_BUS_UART1>;
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+ resets = <&ccu RST_BUS_UART1>;
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status = "disabled";
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};
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@@ -356,8 +511,8 @@
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interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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- clocks = <&ccu 69>;
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- resets = <&ccu 48>;
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+ clocks = <&ccu CLK_BUS_UART2>;
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+ resets = <&ccu RST_BUS_UART2>;
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status = "disabled";
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};
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@@ -367,8 +522,8 @@
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interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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- clocks = <&ccu 70>;
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- resets = <&ccu 49>;
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+ clocks = <&ccu CLK_BUS_UART3>;
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+ resets = <&ccu RST_BUS_UART3>;
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status = "disabled";
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};
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@@ -378,8 +533,8 @@
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interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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- clocks = <&ccu 71>;
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- resets = <&ccu 50>;
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+ clocks = <&ccu CLK_BUS_UART4>;
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+ resets = <&ccu RST_BUS_UART4>;
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status = "disabled";
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};
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@@ -387,8 +542,8 @@
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compatible = "allwinner,sun6i-a31-i2c";
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reg = <0x01c2ac00 0x400>;
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interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
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- clocks = <&ccu 63>;
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- resets = <&ccu 42>;
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+ clocks = <&ccu CLK_BUS_I2C0>;
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+ resets = <&ccu RST_BUS_I2C0>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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@@ -398,8 +553,8 @@
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compatible = "allwinner,sun6i-a31-i2c";
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reg = <0x01c2b000 0x400>;
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interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
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- clocks = <&ccu 64>;
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- resets = <&ccu 43>;
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+ clocks = <&ccu CLK_BUS_I2C1>;
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+ resets = <&ccu RST_BUS_I2C1>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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@@ -409,11 +564,67 @@
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compatible = "allwinner,sun6i-a31-i2c";
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reg = <0x01c2b400 0x400>;
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
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- clocks = <&ccu 65>;
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- resets = <&ccu 44>;
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+ clocks = <&ccu CLK_BUS_I2C2>;
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+ resets = <&ccu RST_BUS_I2C2>;
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+ status = "disabled";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ };
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+
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+
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+ spi0: spi@1c68000 {
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+ compatible = "allwinner,sun8i-h3-spi";
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+ reg = <0x01c68000 0x1000>;
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+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
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+ clock-names = "ahb", "mod";
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+ dmas = <&dma 23>, <&dma 23>;
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+ dma-names = "rx", "tx";
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&spi0_pins>;
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+ resets = <&ccu RST_BUS_SPI0>;
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+ status = "disabled";
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+ num-cs = <1>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ };
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+
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+ spi1: spi@1c69000 {
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+ compatible = "allwinner,sun8i-h3-spi";
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+ reg = <0x01c69000 0x1000>;
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+ interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
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+ clock-names = "ahb", "mod";
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+ dmas = <&dma 24>, <&dma 24>;
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+ dma-names = "rx", "tx";
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&spi1_pins>;
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+ resets = <&ccu RST_BUS_SPI1>;
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+ status = "disabled";
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+ num-cs = <1>;
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|
+ #address-cells = <1>;
|
|
|
+ #size-cells = <0>;
|
|
|
+ };
|
|
|
+
|
|
|
+ emac: ethernet@1c30000 {
|
|
|
+ compatible = "allwinner,sun50i-a64-emac";
|
|
|
+ syscon = <&syscon>;
|
|
|
+ reg = <0x01c30000 0x10000>;
|
|
|
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ interrupt-names = "macirq";
|
|
|
+ resets = <&ccu RST_BUS_EMAC>;
|
|
|
+ reset-names = "stmmaceth";
|
|
|
+ clocks = <&ccu CLK_BUS_EMAC>;
|
|
|
+ clock-names = "stmmaceth";
|
|
|
status = "disabled";
|
|
|
#address-cells = <1>;
|
|
|
#size-cells = <0>;
|
|
|
+
|
|
|
+ mdio: mdio {
|
|
|
+ compatible = "snps,dwmac-mdio";
|
|
|
+ #address-cells = <1>;
|
|
|
+ #size-cells = <0>;
|
|
|
+ };
|
|
|
};
|
|
|
|
|
|
gic: interrupt-controller@1c81000 {
|
|
@@ -434,25 +645,61 @@
|
|
|
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
};
|
|
|
|
|
|
+ r_intc: interrupt-controller@1f00c00 {
|
|
|
+ compatible = "allwinner,sun50i-a64-r-intc",
|
|
|
+ "allwinner,sun6i-a31-r-intc";
|
|
|
+ interrupt-controller;
|
|
|
+ #interrupt-cells = <2>;
|
|
|
+ reg = <0x01f00c00 0x400>;
|
|
|
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ };
|
|
|
+
|
|
|
r_ccu: clock@1f01400 {
|
|
|
compatible = "allwinner,sun50i-a64-r-ccu";
|
|
|
reg = <0x01f01400 0x100>;
|
|
|
- clocks = <&osc24M>, <&osc32k>, <&iosc>;
|
|
|
- clock-names = "hosc", "losc", "iosc";
|
|
|
+ clocks = <&osc24M>, <&osc32k>, <&iosc>,
|
|
|
+ <&ccu 11>;
|
|
|
+ clock-names = "hosc", "losc", "iosc", "pll-periph";
|
|
|
#clock-cells = <1>;
|
|
|
#reset-cells = <1>;
|
|
|
};
|
|
|
|
|
|
- r_pio: pinctrl@01f02c00 {
|
|
|
+ r_pio: pinctrl@1f02c00 {
|
|
|
compatible = "allwinner,sun50i-a64-r-pinctrl";
|
|
|
reg = <0x01f02c00 0x400>;
|
|
|
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
- clocks = <&r_ccu 3>, <&osc24M>, <&osc32k>;
|
|
|
+ clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
|
|
|
clock-names = "apb", "hosc", "losc";
|
|
|
gpio-controller;
|
|
|
#gpio-cells = <3>;
|
|
|
interrupt-controller;
|
|
|
#interrupt-cells = <3>;
|
|
|
+
|
|
|
+ r_rsb_pins: rsb {
|
|
|
+ pins = "PL0", "PL1";
|
|
|
+ function = "s_rsb";
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ r_rsb: rsb@1f03400 {
|
|
|
+ compatible = "allwinner,sun8i-a23-rsb";
|
|
|
+ reg = <0x01f03400 0x400>;
|
|
|
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ clocks = <&r_ccu 6>;
|
|
|
+ clock-frequency = <3000000>;
|
|
|
+ resets = <&r_ccu 2>;
|
|
|
+ pinctrl-names = "default";
|
|
|
+ pinctrl-0 = <&r_rsb_pins>;
|
|
|
+ status = "disabled";
|
|
|
+ #address-cells = <1>;
|
|
|
+ #size-cells = <0>;
|
|
|
+ };
|
|
|
+
|
|
|
+ wdt0: watchdog@1c20ca0 {
|
|
|
+ compatible = "allwinner,sun50i-a64-wdt",
|
|
|
+ "allwinner,sun6i-a31-wdt";
|
|
|
+ reg = <0x01c20ca0 0x20>;
|
|
|
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
};
|
|
|
};
|
|
|
};
|