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@@ -61,6 +61,21 @@ ENTRY(_start)
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1:
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#endif
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+#ifdef CONFIG_ISA_ARCV2
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+ ; In case of DSP extension presence in HW some instructions
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+ ; (related to integer multiply, multiply-accumulate, and divide
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+ ; operation) executes on this DSP execution unit. So their
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+ ; execution will depend on dsp configuration register (DSP_CTRL)
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+ ; As we want these instructions to execute the same way regardless
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+ ; of DSP presence we need to set DSP_CTRL properly.
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+ lr r5, [ARC_AUX_DSP_BUILD]
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+ bmsk r5, r5, 7
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+ breq r5, 0, 1f
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+ mov r5, 0
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+ sr r5, [ARC_AUX_DSP_CTRL]
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+1:
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+#endif
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+
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#ifdef __ARC_UNALIGNED__
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/*
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* Enable handling of unaligned access in the CPU as by default
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