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@@ -1,17 +1,16 @@
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+.. SPDX-License-Identifier: GPL-2.0+
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+
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+MIPS
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+====
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Notes for the MIPS architecture port of U-Boot
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Toolchains
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----------
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- http://www.denx.de/wiki/DULG/ELDK
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- ELDK < DULG < DENX
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-
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- http://www.emdebian.org/crosstools.html
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- Embedded Debian -- Cross-development toolchains
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-
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- http://buildroot.uclibc.org/
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- Buildroot
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+ * `ELDK < DULG < DENX <http://www.denx.de/wiki/DULG/ELDK>`_
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+ * `Embedded Debian -- Cross-development toolchains <http://www.emdebian.org/crosstools.html>`_
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+ * `Buildroot <http://buildroot.uclibc.org/>`_
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Known Issues
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------------
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@@ -24,9 +23,9 @@ Known Issues
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re-initializes the cache. The more common uImage 'bootm' command does
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not suffer this problem.
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- [workaround] To avoid this cache incoherency,
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- 1) insert flush_cache(all) before calling dcache_disable(), or
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- 2) fix dcache_disable() to do both flushing and disabling cache.
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+ [workaround] To avoid this cache incoherency:
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+ - insert flush_cache(all) before calling dcache_disable(), or
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+ - fix dcache_disable() to do both flushing and disabling cache.
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* Note that Linux users need to kill dcache_disable() in do_bootelf_exec()
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or override do_bootelf_exec() not to disable I-/D-caches, because most
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@@ -36,19 +35,12 @@ TODOs
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-----
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* Probe CPU types, I-/D-cache and TLB size etc. automatically
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-
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* Secondary cache support missing
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-
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* Initialize TLB entries redardless of their use
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-
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* R2000/R3000 class parts are not supported
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-
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* Limited testing across different MIPS variants
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-
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* Due to cache initialization issues, the DRAM on board must be
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initialized in board specific assembler language before the cache init
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code is run -- that is, initialize the DRAM in lowlevel_init().
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-
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* centralize/share more CPU code of MIPS32, MIPS64 and XBurst
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-
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* support Qemu Malta
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