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@@ -6,23 +6,28 @@
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*
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* Copyright (C) 2004-2009 Freescale Semiconductor, Inc.
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* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
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+ *
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+ * Support for DM and DT, non-DM code removed.
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+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
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+ *
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+ * TODO: fsl_dspi.c should work as a driver for the DSPI module.
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*/
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#include <common.h>
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+#include <dm.h>
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+#include <dm/platform_data/spi_coldfire.h>
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#include <spi.h>
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#include <malloc.h>
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-#include <asm/immap.h>
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+#include <asm/coldfire/dspi.h>
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+#include <asm/io.h>
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-struct cf_spi_slave {
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- struct spi_slave slave;
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+struct coldfire_spi_priv {
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+ struct dspi *regs;
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uint baudrate;
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+ int mode;
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int charbit;
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};
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-extern void cfspi_port_conf(void);
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-extern int cfspi_claim_bus(uint bus, uint cs);
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-extern void cfspi_release_bus(uint bus, uint cs);
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-
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DECLARE_GLOBAL_DATA_PTR;
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#ifndef CONFIG_SPI_IDLE_VAL
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@@ -33,163 +38,193 @@ DECLARE_GLOBAL_DATA_PTR;
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#endif
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#endif
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-#if defined(CONFIG_CF_DSPI)
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-/* DSPI specific mode */
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-#define SPI_MODE_MOD 0x00200000
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-#define SPI_DBLRATE 0x00100000
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-
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-static inline struct cf_spi_slave *to_cf_spi_slave(struct spi_slave *slave)
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+/*
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+ * DSPI specific mode
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+ *
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+ * bit 31 - 28: Transfer size 3 to 16 bits
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+ * 27 - 26: PCS to SCK delay prescaler
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+ * 25 - 24: After SCK delay prescaler
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+ * 23 - 22: Delay after transfer prescaler
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+ * 21 : Allow overwrite for bit 31-22 and bit 20-8
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+ * 20 : Double baud rate
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+ * 19 - 16: PCS to SCK delay scaler
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+ * 15 - 12: After SCK delay scaler
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+ * 11 - 8: Delay after transfer scaler
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+ * 7 - 0: SPI_CPHA, SPI_CPOL, SPI_LSB_FIRST
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+ */
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+#define SPI_MODE_MOD 0x00200000
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+#define SPI_MODE_DBLRATE 0x00100000
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+
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+#define SPI_MODE_XFER_SZ_MASK 0xf0000000
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+#define SPI_MODE_DLY_PRE_MASK 0x0fc00000
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+#define SPI_MODE_DLY_SCA_MASK 0x000fff00
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+
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+#define MCF_FRM_SZ_16BIT DSPI_CTAR_TRSZ(0xf)
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+#define MCF_DSPI_SPEED_BESTMATCH 0x7FFFFFFF
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+#define MCF_DSPI_MAX_CTAR_REGS 8
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+
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+/* Default values */
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+#define MCF_DSPI_DEFAULT_SCK_FREQ 10000000
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+#define MCF_DSPI_DEFAULT_MAX_CS 4
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+#define MCF_DSPI_DEFAULT_MODE 0
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+
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+#define MCF_DSPI_DEFAULT_CTAR (DSPI_CTAR_TRSZ(7) | \
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+ DSPI_CTAR_PCSSCK_1CLK | \
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+ DSPI_CTAR_PASC(0) | \
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+ DSPI_CTAR_PDT(0) | \
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+ DSPI_CTAR_CSSCK(0) | \
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+ DSPI_CTAR_ASC(0) | \
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+ DSPI_CTAR_DT(1) | \
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+ DSPI_CTAR_BR(6))
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+
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+#define MCF_CTAR_MODE_MASK (MCF_FRM_SZ_16BIT | \
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+ DSPI_CTAR_PCSSCK(3) | \
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+ DSPI_CTAR_PASC_7CLK | \
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+ DSPI_CTAR_PDT(3) | \
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+ DSPI_CTAR_CSSCK(0x0f) | \
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+ DSPI_CTAR_ASC(0x0f) | \
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+ DSPI_CTAR_DT(0x0f))
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+
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+#define setup_ctrl(ctrl, cs) ((ctrl & 0xFF000000) | ((1 << cs) << 16))
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+
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+static inline void cfspi_tx(struct coldfire_spi_priv *cfspi,
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+ u32 ctrl, u16 data)
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{
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- return container_of(slave, struct cf_spi_slave, slave);
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+ /*
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+ * Need to check fifo level here
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+ */
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+ while ((readl(&cfspi->regs->sr) & 0x0000F000) >= 0x4000)
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+ ;
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+
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+ writel(ctrl | data, &cfspi->regs->tfr);
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}
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-static void cfspi_init(void)
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+static inline u16 cfspi_rx(struct coldfire_spi_priv *cfspi)
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{
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- volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
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- cfspi_port_conf(); /* port configuration */
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-
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- dspi->mcr = DSPI_MCR_MSTR | DSPI_MCR_CSIS7 | DSPI_MCR_CSIS6 |
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- DSPI_MCR_CSIS5 | DSPI_MCR_CSIS4 | DSPI_MCR_CSIS3 |
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- DSPI_MCR_CSIS2 | DSPI_MCR_CSIS1 | DSPI_MCR_CSIS0 |
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- DSPI_MCR_CRXF | DSPI_MCR_CTXF;
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+ while ((readl(&cfspi->regs->sr) & 0x000000F0) == 0)
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+ ;
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- /* Default setting in platform configuration */
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-#ifdef CONFIG_SYS_DSPI_CTAR0
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- dspi->ctar[0] = CONFIG_SYS_DSPI_CTAR0;
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-#endif
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-#ifdef CONFIG_SYS_DSPI_CTAR1
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- dspi->ctar[1] = CONFIG_SYS_DSPI_CTAR1;
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-#endif
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-#ifdef CONFIG_SYS_DSPI_CTAR2
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- dspi->ctar[2] = CONFIG_SYS_DSPI_CTAR2;
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-#endif
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-#ifdef CONFIG_SYS_DSPI_CTAR3
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- dspi->ctar[3] = CONFIG_SYS_DSPI_CTAR3;
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-#endif
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-#ifdef CONFIG_SYS_DSPI_CTAR4
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- dspi->ctar[4] = CONFIG_SYS_DSPI_CTAR4;
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-#endif
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-#ifdef CONFIG_SYS_DSPI_CTAR5
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- dspi->ctar[5] = CONFIG_SYS_DSPI_CTAR5;
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-#endif
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-#ifdef CONFIG_SYS_DSPI_CTAR6
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- dspi->ctar[6] = CONFIG_SYS_DSPI_CTAR6;
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-#endif
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-#ifdef CONFIG_SYS_DSPI_CTAR7
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- dspi->ctar[7] = CONFIG_SYS_DSPI_CTAR7;
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-#endif
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+ return readw(&cfspi->regs->rfr);
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}
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-static void cfspi_tx(u32 ctrl, u16 data)
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+static int coldfire_spi_claim_bus(struct udevice *dev)
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{
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- volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
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+ struct udevice *bus = dev->parent;
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+ struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
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+ struct dspi *dspi = cfspi->regs;
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+ struct dm_spi_slave_platdata *slave_plat =
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+ dev_get_parent_platdata(dev);
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- while ((dspi->sr & 0x0000F000) >= 4) ;
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+ if ((in_be32(&dspi->sr) & DSPI_SR_TXRXS) != DSPI_SR_TXRXS)
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+ return -1;
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- dspi->tfr = (ctrl | data);
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+ /* Clear FIFO and resume transfer */
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+ clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);
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+
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+ dspi_chip_select(slave_plat->cs);
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+
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+ return 0;
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}
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-static u16 cfspi_rx(void)
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+static int coldfire_spi_release_bus(struct udevice *dev)
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{
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- volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
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+ struct udevice *bus = dev->parent;
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+ struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
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+ struct dspi *dspi = cfspi->regs;
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+ struct dm_spi_slave_platdata *slave_plat =
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+ dev_get_parent_platdata(dev);
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- while ((dspi->sr & 0x000000F0) == 0) ;
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+ /* Clear FIFO */
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+ clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);
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- return (dspi->rfr & 0xFFFF);
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+ dspi_chip_unselect(slave_plat->cs);
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+
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+ return 0;
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}
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-static int cfspi_xfer(struct spi_slave *slave, uint bitlen, const void *dout,
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- void *din, ulong flags)
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+static int coldfire_spi_xfer(struct udevice *dev, unsigned int bitlen,
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+ const void *dout, void *din,
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+ unsigned long flags)
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{
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- struct cf_spi_slave *cfslave = to_cf_spi_slave(slave);
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+ struct udevice *bus = dev_get_parent(dev);
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+ struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
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+ struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
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u16 *spi_rd16 = NULL, *spi_wr16 = NULL;
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u8 *spi_rd = NULL, *spi_wr = NULL;
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- static u32 ctrl = 0;
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+ static u32 ctrl;
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uint len = bitlen >> 3;
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- if (cfslave->charbit == 16) {
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+ if (cfspi->charbit == 16) {
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bitlen >>= 1;
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- spi_wr16 = (u16 *) dout;
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- spi_rd16 = (u16 *) din;
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+ spi_wr16 = (u16 *)dout;
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+ spi_rd16 = (u16 *)din;
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} else {
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- spi_wr = (u8 *) dout;
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- spi_rd = (u8 *) din;
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+ spi_wr = (u8 *)dout;
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+ spi_rd = (u8 *)din;
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}
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if ((flags & SPI_XFER_BEGIN) == SPI_XFER_BEGIN)
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ctrl |= DSPI_TFR_CONT;
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- ctrl = (ctrl & 0xFF000000) | ((1 << slave->cs) << 16);
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+ ctrl = setup_ctrl(ctrl, slave_plat->cs);
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if (len > 1) {
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int tmp_len = len - 1;
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+
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while (tmp_len--) {
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- if (dout != NULL) {
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- if (cfslave->charbit == 16)
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- cfspi_tx(ctrl, *spi_wr16++);
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+ if (dout) {
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+ if (cfspi->charbit == 16)
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+ cfspi_tx(cfspi, ctrl, *spi_wr16++);
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else
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- cfspi_tx(ctrl, *spi_wr++);
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- cfspi_rx();
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+ cfspi_tx(cfspi, ctrl, *spi_wr++);
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+ cfspi_rx(cfspi);
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}
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- if (din != NULL) {
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- cfspi_tx(ctrl, CONFIG_SPI_IDLE_VAL);
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- if (cfslave->charbit == 16)
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- *spi_rd16++ = cfspi_rx();
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+ if (din) {
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+ cfspi_tx(cfspi, ctrl, CONFIG_SPI_IDLE_VAL);
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+ if (cfspi->charbit == 16)
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+ *spi_rd16++ = cfspi_rx(cfspi);
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else
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- *spi_rd++ = cfspi_rx();
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+ *spi_rd++ = cfspi_rx(cfspi);
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}
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}
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len = 1; /* remaining byte */
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}
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- if ((flags & SPI_XFER_END) == SPI_XFER_END)
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+ if (flags & SPI_XFER_END)
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ctrl &= ~DSPI_TFR_CONT;
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if (len) {
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- if (dout != NULL) {
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- if (cfslave->charbit == 16)
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- cfspi_tx(ctrl, *spi_wr16);
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+ if (dout) {
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+ if (cfspi->charbit == 16)
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+ cfspi_tx(cfspi, ctrl, *spi_wr16);
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else
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- cfspi_tx(ctrl, *spi_wr);
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- cfspi_rx();
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+ cfspi_tx(cfspi, ctrl, *spi_wr);
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+ cfspi_rx(cfspi);
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}
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- if (din != NULL) {
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- cfspi_tx(ctrl, CONFIG_SPI_IDLE_VAL);
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- if (cfslave->charbit == 16)
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- *spi_rd16 = cfspi_rx();
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+ if (din) {
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+ cfspi_tx(cfspi, ctrl, CONFIG_SPI_IDLE_VAL);
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+ if (cfspi->charbit == 16)
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+ *spi_rd16 = cfspi_rx(cfspi);
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else
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- *spi_rd = cfspi_rx();
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+ *spi_rd = cfspi_rx(cfspi);
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}
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} else {
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/* dummy read */
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- cfspi_tx(ctrl, CONFIG_SPI_IDLE_VAL);
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- cfspi_rx();
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+ cfspi_tx(cfspi, ctrl, CONFIG_SPI_IDLE_VAL);
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+ cfspi_rx(cfspi);
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}
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return 0;
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}
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-static struct spi_slave *cfspi_setup_slave(struct cf_spi_slave *cfslave,
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- uint mode)
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+static int coldfire_spi_set_speed(struct udevice *bus, uint max_hz)
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{
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- /*
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- * bit definition for mode:
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- * bit 31 - 28: Transfer size 3 to 16 bits
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- * 27 - 26: PCS to SCK delay prescaler
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- * 25 - 24: After SCK delay prescaler
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- * 23 - 22: Delay after transfer prescaler
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- * 21 : Allow overwrite for bit 31-22 and bit 20-8
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- * 20 : Double baud rate
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- * 19 - 16: PCS to SCK delay scaler
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- * 15 - 12: After SCK delay scaler
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- * 11 - 8: Delay after transfer scaler
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- * 7 - 0: SPI_CPHA, SPI_CPOL, SPI_LSB_FIRST
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- */
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- volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
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+ struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
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+ struct dspi *dspi = cfspi->regs;
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int prescaler[] = { 2, 3, 5, 7 };
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int scaler[] = {
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2, 4, 6, 8,
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@@ -198,57 +233,41 @@ static struct spi_slave *cfspi_setup_slave(struct cf_spi_slave *cfslave,
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4096, 8192, 16384, 32768
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};
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int i, j, pbrcnt, brcnt, diff, tmp, dbr = 0;
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- int best_i, best_j, bestmatch = 0x7FFFFFFF, baud_speed;
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- u32 bus_setup = 0;
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+ int best_i, best_j, bestmatch = MCF_DSPI_SPEED_BESTMATCH, baud_speed;
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+ u32 bus_setup;
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+
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+ cfspi->baudrate = max_hz;
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+
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+ /* Read current setup */
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+ bus_setup = readl(&dspi->ctar[bus->seq]);
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tmp = (prescaler[3] * scaler[15]);
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/* Maximum and minimum baudrate it can handle */
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- if ((cfslave->baudrate > (gd->bus_clk >> 1)) ||
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- (cfslave->baudrate < (gd->bus_clk / tmp))) {
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+ if ((cfspi->baudrate > (gd->bus_clk >> 1)) ||
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+ (cfspi->baudrate < (gd->bus_clk / tmp))) {
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printf("Exceed baudrate limitation: Max %d - Min %d\n",
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(int)(gd->bus_clk >> 1), (int)(gd->bus_clk / tmp));
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- return NULL;
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+ return -1;
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}
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/* Activate Double Baud when it exceed 1/4 the bus clk */
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- if ((CONFIG_SYS_DSPI_CTAR0 & DSPI_CTAR_DBR) ||
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- (cfslave->baudrate > (gd->bus_clk / (prescaler[0] * scaler[0])))) {
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+ if ((bus_setup & DSPI_CTAR_DBR) ||
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+ (cfspi->baudrate > (gd->bus_clk / (prescaler[0] * scaler[0])))) {
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bus_setup |= DSPI_CTAR_DBR;
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dbr = 1;
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}
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- if (mode & SPI_CPOL)
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- bus_setup |= DSPI_CTAR_CPOL;
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- if (mode & SPI_CPHA)
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- bus_setup |= DSPI_CTAR_CPHA;
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- if (mode & SPI_LSB_FIRST)
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- bus_setup |= DSPI_CTAR_LSBFE;
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-
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/* Overwrite default value set in platform configuration file */
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- if (mode & SPI_MODE_MOD) {
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-
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- if ((mode & 0xF0000000) == 0)
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- bus_setup |=
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- dspi->ctar[cfslave->slave.bus] & 0x78000000;
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- else
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- bus_setup |= ((mode & 0xF0000000) >> 1);
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-
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|
|
+ if (cfspi->mode & SPI_MODE_MOD) {
|
|
|
/*
|
|
|
* Check to see if it is enabled by default in platform
|
|
|
* config, or manual setting passed by mode parameter
|
|
|
*/
|
|
|
- if (mode & SPI_DBLRATE) {
|
|
|
+ if (cfspi->mode & SPI_MODE_DBLRATE) {
|
|
|
bus_setup |= DSPI_CTAR_DBR;
|
|
|
dbr = 1;
|
|
|
}
|
|
|
- bus_setup |= (mode & 0x0FC00000) >> 4; /* PSCSCK, PASC, PDT */
|
|
|
- bus_setup |= (mode & 0x000FFF00) >> 4; /* CSSCK, ASC, DT */
|
|
|
- } else
|
|
|
- bus_setup |= (dspi->ctar[cfslave->slave.bus] & 0x78FCFFF0);
|
|
|
-
|
|
|
- cfslave->charbit =
|
|
|
- ((dspi->ctar[cfslave->slave.bus] & 0x78000000) ==
|
|
|
- 0x78000000) ? 16 : 8;
|
|
|
+ }
|
|
|
|
|
|
pbrcnt = sizeof(prescaler) / sizeof(int);
|
|
|
brcnt = sizeof(scaler) / sizeof(int);
|
|
@@ -259,10 +278,10 @@ static struct spi_slave *cfspi_setup_slave(struct cf_spi_slave *cfslave,
|
|
|
for (j = 0; j < brcnt; j++) {
|
|
|
tmp = (baud_speed / scaler[j]) * (1 + dbr);
|
|
|
|
|
|
- if (tmp > cfslave->baudrate)
|
|
|
- diff = tmp - cfslave->baudrate;
|
|
|
+ if (tmp > cfspi->baudrate)
|
|
|
+ diff = tmp - cfspi->baudrate;
|
|
|
else
|
|
|
- diff = cfslave->baudrate - tmp;
|
|
|
+ diff = cfspi->baudrate - tmp;
|
|
|
|
|
|
if (diff < bestmatch) {
|
|
|
bestmatch = diff;
|
|
@@ -271,65 +290,174 @@ static struct spi_slave *cfspi_setup_slave(struct cf_spi_slave *cfslave,
|
|
|
}
|
|
|
}
|
|
|
}
|
|
|
+
|
|
|
+ bus_setup &= ~(DSPI_CTAR_PBR(0x03) | DSPI_CTAR_BR(0x0f));
|
|
|
bus_setup |= (DSPI_CTAR_PBR(best_i) | DSPI_CTAR_BR(best_j));
|
|
|
- dspi->ctar[cfslave->slave.bus] = bus_setup;
|
|
|
+ writel(bus_setup, &dspi->ctar[bus->seq]);
|
|
|
|
|
|
- return &cfslave->slave;
|
|
|
+ return 0;
|
|
|
}
|
|
|
-#endif /* CONFIG_CF_DSPI */
|
|
|
|
|
|
-#ifdef CONFIG_CMD_SPI
|
|
|
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
|
|
|
+static int coldfire_spi_set_mode(struct udevice *bus, uint mode)
|
|
|
{
|
|
|
- if (((cs >= 0) && (cs < 8)) && ((bus >= 0) && (bus < 8)))
|
|
|
- return 1;
|
|
|
- else
|
|
|
- return 0;
|
|
|
-}
|
|
|
+ struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
|
|
|
+ struct dspi *dspi = cfspi->regs;
|
|
|
+ u32 bus_setup = 0;
|
|
|
|
|
|
-void spi_init(void)
|
|
|
-{
|
|
|
- cfspi_init();
|
|
|
-}
|
|
|
+ cfspi->mode = mode;
|
|
|
|
|
|
-struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
|
|
|
- unsigned int max_hz, unsigned int mode)
|
|
|
-{
|
|
|
- struct cf_spi_slave *cfslave;
|
|
|
+ if (cfspi->mode & SPI_CPOL)
|
|
|
+ bus_setup |= DSPI_CTAR_CPOL;
|
|
|
+ if (cfspi->mode & SPI_CPHA)
|
|
|
+ bus_setup |= DSPI_CTAR_CPHA;
|
|
|
+ if (cfspi->mode & SPI_LSB_FIRST)
|
|
|
+ bus_setup |= DSPI_CTAR_LSBFE;
|
|
|
|
|
|
- if (!spi_cs_is_valid(bus, cs))
|
|
|
- return NULL;
|
|
|
+ /* Overwrite default value set in platform configuration file */
|
|
|
+ if (cfspi->mode & SPI_MODE_MOD) {
|
|
|
+ if ((cfspi->mode & SPI_MODE_XFER_SZ_MASK) == 0)
|
|
|
+ bus_setup |=
|
|
|
+ readl(&dspi->ctar[bus->seq]) & MCF_FRM_SZ_16BIT;
|
|
|
+ else
|
|
|
+ bus_setup |=
|
|
|
+ ((cfspi->mode & SPI_MODE_XFER_SZ_MASK) >> 1);
|
|
|
|
|
|
- cfslave = spi_alloc_slave(struct cf_spi_slave, bus, cs);
|
|
|
- if (!cfslave)
|
|
|
- return NULL;
|
|
|
+ /* PSCSCK, PASC, PDT */
|
|
|
+ bus_setup |= (cfspi->mode & SPI_MODE_DLY_PRE_MASK) >> 4;
|
|
|
+ /* CSSCK, ASC, DT */
|
|
|
+ bus_setup |= (cfspi->mode & SPI_MODE_DLY_SCA_MASK) >> 4;
|
|
|
+ } else {
|
|
|
+ bus_setup |=
|
|
|
+ (readl(&dspi->ctar[bus->seq]) & MCF_CTAR_MODE_MASK);
|
|
|
+ }
|
|
|
+
|
|
|
+ cfspi->charbit =
|
|
|
+ ((readl(&dspi->ctar[bus->seq]) & MCF_FRM_SZ_16BIT) ==
|
|
|
+ MCF_FRM_SZ_16BIT) ? 16 : 8;
|
|
|
|
|
|
- cfslave->baudrate = max_hz;
|
|
|
+ setbits_be32(&dspi->ctar[bus->seq], bus_setup);
|
|
|
|
|
|
- /* specific setup */
|
|
|
- return cfspi_setup_slave(cfslave, mode);
|
|
|
+ return 0;
|
|
|
}
|
|
|
|
|
|
-void spi_free_slave(struct spi_slave *slave)
|
|
|
+static int coldfire_spi_probe(struct udevice *bus)
|
|
|
{
|
|
|
- struct cf_spi_slave *cfslave = to_cf_spi_slave(slave);
|
|
|
+ struct coldfire_spi_platdata *plat = dev_get_platdata(bus);
|
|
|
+ struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
|
|
|
+ struct dspi *dspi = cfspi->regs;
|
|
|
+ int i;
|
|
|
|
|
|
- free(cfslave);
|
|
|
-}
|
|
|
+ cfspi->regs = (struct dspi *)plat->regs_addr;
|
|
|
|
|
|
-int spi_claim_bus(struct spi_slave *slave)
|
|
|
-{
|
|
|
- return cfspi_claim_bus(slave->bus, slave->cs);
|
|
|
+ cfspi->baudrate = plat->speed_hz;
|
|
|
+ cfspi->mode = plat->mode;
|
|
|
+
|
|
|
+ for (i = 0; i < MCF_DSPI_MAX_CTAR_REGS; i++) {
|
|
|
+ unsigned int ctar = 0;
|
|
|
+
|
|
|
+ if (plat->ctar[i][0] == 0)
|
|
|
+ break;
|
|
|
+
|
|
|
+ ctar = DSPI_CTAR_TRSZ(plat->ctar[i][0]) |
|
|
|
+ DSPI_CTAR_PCSSCK(plat->ctar[i][1]) |
|
|
|
+ DSPI_CTAR_PASC(plat->ctar[i][2]) |
|
|
|
+ DSPI_CTAR_PDT(plat->ctar[i][3]) |
|
|
|
+ DSPI_CTAR_CSSCK(plat->ctar[i][4]) |
|
|
|
+ DSPI_CTAR_ASC(plat->ctar[i][5]) |
|
|
|
+ DSPI_CTAR_DT(plat->ctar[i][6]) |
|
|
|
+ DSPI_CTAR_BR(plat->ctar[i][7]);
|
|
|
+
|
|
|
+ writel(ctar, &cfspi->regs->ctar[i]);
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Default CTARs */
|
|
|
+ for (i = 0; i < MCF_DSPI_MAX_CTAR_REGS; i++)
|
|
|
+ writel(MCF_DSPI_DEFAULT_CTAR, &dspi->ctar[i]);
|
|
|
+
|
|
|
+ dspi->mcr = DSPI_MCR_MSTR | DSPI_MCR_CSIS7 | DSPI_MCR_CSIS6 |
|
|
|
+ DSPI_MCR_CSIS5 | DSPI_MCR_CSIS4 | DSPI_MCR_CSIS3 |
|
|
|
+ DSPI_MCR_CSIS2 | DSPI_MCR_CSIS1 | DSPI_MCR_CSIS0 |
|
|
|
+ DSPI_MCR_CRXF | DSPI_MCR_CTXF;
|
|
|
+
|
|
|
+ return 0;
|
|
|
}
|
|
|
|
|
|
-void spi_release_bus(struct spi_slave *slave)
|
|
|
+void spi_init(void)
|
|
|
{
|
|
|
- cfspi_release_bus(slave->bus, slave->cs);
|
|
|
}
|
|
|
|
|
|
-int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
|
|
|
- void *din, unsigned long flags)
|
|
|
+#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
|
|
|
+static int coldfire_dspi_ofdata_to_platdata(struct udevice *bus)
|
|
|
{
|
|
|
- return cfspi_xfer(slave, bitlen, dout, din, flags);
|
|
|
+ fdt_addr_t addr;
|
|
|
+ struct coldfire_spi_platdata *plat = bus->platdata;
|
|
|
+ const void *blob = gd->fdt_blob;
|
|
|
+ int node = dev_of_offset(bus);
|
|
|
+ int *ctar, len;
|
|
|
+
|
|
|
+ addr = devfdt_get_addr(bus);
|
|
|
+ if (addr == FDT_ADDR_T_NONE)
|
|
|
+ return -ENOMEM;
|
|
|
+
|
|
|
+ plat->regs_addr = addr;
|
|
|
+
|
|
|
+ plat->num_cs = fdtdec_get_int(blob, node, "num-cs",
|
|
|
+ MCF_DSPI_DEFAULT_MAX_CS);
|
|
|
+
|
|
|
+ plat->speed_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
|
|
|
+ MCF_DSPI_DEFAULT_SCK_FREQ);
|
|
|
+
|
|
|
+ plat->mode = fdtdec_get_int(blob, node, "spi-mode",
|
|
|
+ MCF_DSPI_DEFAULT_MODE);
|
|
|
+
|
|
|
+ memset(plat->ctar, 0, sizeof(plat->ctar));
|
|
|
+
|
|
|
+ ctar = (int *)fdt_getprop(blob, node, "ctar-params", &len);
|
|
|
+
|
|
|
+ if (ctar && len) {
|
|
|
+ int i, q, ctar_regs;
|
|
|
+
|
|
|
+ ctar_regs = len / sizeof(unsigned int) / MAX_CTAR_FIELDS;
|
|
|
+
|
|
|
+ if (ctar_regs > MAX_CTAR_REGS)
|
|
|
+ ctar_regs = MAX_CTAR_REGS;
|
|
|
+
|
|
|
+ for (i = 0; i < ctar_regs; i++) {
|
|
|
+ for (q = 0; q < MAX_CTAR_FIELDS; q++)
|
|
|
+ plat->ctar[i][q] = *ctar++;
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ debug("DSPI: regs=%pa, max-frequency=%d, num-cs=%d, mode=%d\n",
|
|
|
+ (void *)plat->regs_addr,
|
|
|
+ plat->speed_hz, plat->num_cs, plat->mode);
|
|
|
+
|
|
|
+ return 0;
|
|
|
}
|
|
|
-#endif /* CONFIG_CMD_SPI */
|
|
|
+
|
|
|
+static const struct udevice_id coldfire_spi_ids[] = {
|
|
|
+ { .compatible = "fsl,mcf-dspi" },
|
|
|
+ { }
|
|
|
+};
|
|
|
+#endif
|
|
|
+
|
|
|
+static const struct dm_spi_ops coldfire_spi_ops = {
|
|
|
+ .claim_bus = coldfire_spi_claim_bus,
|
|
|
+ .release_bus = coldfire_spi_release_bus,
|
|
|
+ .xfer = coldfire_spi_xfer,
|
|
|
+ .set_speed = coldfire_spi_set_speed,
|
|
|
+ .set_mode = coldfire_spi_set_mode,
|
|
|
+};
|
|
|
+
|
|
|
+U_BOOT_DRIVER(coldfire_spi) = {
|
|
|
+ .name = "spi_coldfire",
|
|
|
+ .id = UCLASS_SPI,
|
|
|
+#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
|
|
|
+ .of_match = coldfire_spi_ids,
|
|
|
+ .ofdata_to_platdata = coldfire_dspi_ofdata_to_platdata,
|
|
|
+ .platdata_auto_alloc_size = sizeof(struct coldfire_spi_platdata),
|
|
|
+#endif
|
|
|
+ .probe = coldfire_spi_probe,
|
|
|
+ .ops = &coldfire_spi_ops,
|
|
|
+ .priv_auto_alloc_size = sizeof(struct coldfire_spi_priv),
|
|
|
+};
|