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@@ -93,6 +93,7 @@ struct ls_pcie {
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void __iomem *dbi;
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void __iomem *va_cfg0;
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void __iomem *va_cfg1;
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+ int next_lut_index;
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struct pci_controller hose;
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};
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@@ -482,6 +483,147 @@ static void ls_pcie_setup_ep(struct ls_pcie *pcie, struct ls_pcie_info *info)
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}
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}
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+#ifdef CONFIG_FSL_LSCH3
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+/*
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+ * Return next available LUT index.
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+ */
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+static int ls_pcie_next_lut_index(struct ls_pcie *pcie)
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+{
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+ if (pcie->next_lut_index < PCIE_LUT_ENTRY_COUNT)
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+ return pcie->next_lut_index++;
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+ else
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+ return -1; /* LUT is full */
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+}
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+
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+/*
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+ * Program a single LUT entry
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+ */
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+static void ls_pcie_lut_set_mapping(struct ls_pcie *pcie, int index, u32 devid,
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+ u32 streamid)
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+{
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+ void __iomem *lut;
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+
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+ lut = pcie->dbi + PCIE_LUT_BASE;
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+
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+ /* leave mask as all zeroes, want to match all bits */
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+ writel((devid << 16), lut + PCIE_LUT_UDR(index));
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+ writel(streamid | PCIE_LUT_ENABLE, lut + PCIE_LUT_LDR(index));
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+}
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+
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+/* returns the next available streamid */
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+static u32 ls_pcie_next_streamid(void)
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+{
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+ static int next_stream_id = FSL_PEX_STREAM_ID_START;
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+
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+ if (next_stream_id > FSL_PEX_STREAM_ID_END)
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+ return 0xffffffff;
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+
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+ return next_stream_id++;
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+}
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+
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+/*
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+ * An msi-map is a property to be added to the pci controller
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+ * node. It is a table, where each entry consists of 4 fields
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+ * e.g.:
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+ *
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+ * msi-map = <[devid] [phandle-to-msi-ctrl] [stream-id] [count]
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+ * [devid] [phandle-to-msi-ctrl] [stream-id] [count]>;
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+ */
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+static void fdt_pcie_set_msi_map_entry(void *blob, struct ls_pcie *pcie,
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+ u32 devid, u32 streamid)
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+{
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+ char pcie_path[19];
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+ u32 *prop;
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+ u32 phandle;
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+ int nodeoffset;
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+
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+ /* find pci controller node */
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+ snprintf(pcie_path, sizeof(pcie_path), "/soc/pcie@%llx",
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+ (u64)pcie->dbi);
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+ nodeoffset = fdt_path_offset(blob, pcie_path);
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+ if (nodeoffset < 0) {
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+ printf("\n%s: ERROR: unable to update PCIe node: %s\n",
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+ __func__, pcie_path);
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+ return;
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+ }
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+
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+ /* get phandle to MSI controller */
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+ prop = (u32 *)fdt_getprop(blob, nodeoffset, "msi-parent", 0);
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+ if (prop == NULL) {
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+ printf("\n%s: ERROR: missing msi-parent: %s\n", __func__,
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+ pcie_path);
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+ return;
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+ }
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+ phandle = be32_to_cpu(*prop);
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+
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+ /* set one msi-map row */
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+ fdt_appendprop_u32(blob, nodeoffset, "msi-map", devid);
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+ fdt_appendprop_u32(blob, nodeoffset, "msi-map", phandle);
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+ fdt_appendprop_u32(blob, nodeoffset, "msi-map", streamid);
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+ fdt_appendprop_u32(blob, nodeoffset, "msi-map", 1);
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+}
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+
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+static void fdt_fixup_pcie(void *blob)
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+{
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+ unsigned int found_multi = 0;
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+ unsigned char header_type;
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+ int index;
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+ u32 streamid;
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+ pci_dev_t dev;
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+ int bus;
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+ unsigned short id;
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+ struct pci_controller *hose;
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+ struct ls_pcie *pcie;
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+ int i;
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+
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+ for (i = 0, hose = pci_get_hose_head(); hose; hose = hose->next, i++) {
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+ pcie = hose->priv_data;
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+ for (bus = hose->first_busno; bus <= hose->last_busno; bus++) {
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+
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+ for (dev = PCI_BDF(bus, 0, 0);
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+ dev < PCI_BDF(bus, PCI_MAX_PCI_DEVICES - 1,
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+ PCI_MAX_PCI_FUNCTIONS - 1);
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+ dev += PCI_BDF(0, 0, 1)) {
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+
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+ if (PCI_FUNC(dev) && !found_multi)
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+ continue;
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+
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+ pci_read_config_word(dev, PCI_VENDOR_ID, &id);
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+
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+ pci_read_config_byte(dev, PCI_HEADER_TYPE,
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+ &header_type);
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+
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+ if ((id == 0xFFFF) || (id == 0x0000))
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+ continue;
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+
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+ if (!PCI_FUNC(dev))
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+ found_multi = header_type & 0x80;
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+
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+ streamid = ls_pcie_next_streamid();
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+ if (streamid == 0xffffffff) {
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+ printf("ERROR: no stream ids free\n");
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+ continue;
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+ }
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+
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+ index = ls_pcie_next_lut_index(pcie);
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+ if (index < 0) {
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+ printf("ERROR: no LUT indexes free\n");
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+ continue;
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+ }
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+
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+ /* map PCI b.d.f to streamID in LUT */
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+ ls_pcie_lut_set_mapping(pcie, index, dev >> 8,
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+ streamid);
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+
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+ /* update msi-map in device tree */
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+ fdt_pcie_set_msi_map_entry(blob, pcie, dev >> 8,
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+ streamid);
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+ }
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+ }
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+ }
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+}
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+#endif
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+
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int ls_pcie_init_ctrl(int busno, enum srds_prtcl dev, struct ls_pcie_info *info)
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{
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struct ls_pcie *pcie;
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@@ -513,6 +655,7 @@ int ls_pcie_init_ctrl(int busno, enum srds_prtcl dev, struct ls_pcie_info *info)
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pcie->va_cfg1 = map_physmem(info->cfg1_phys,
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info->cfg1_size,
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MAP_NOCACHE);
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+ pcie->next_lut_index = 0;
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/* outbound memory */
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pci_set_region(&hose->regions[0],
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@@ -657,6 +800,10 @@ void ft_pci_setup(void *blob, bd_t *bd)
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#ifdef CONFIG_PCIE4
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ft_pcie_ls_setup(blob, FSL_PCIE_COMPAT, CONFIG_SYS_PCIE4_ADDR, PCIE4);
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#endif
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+
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+ #ifdef CONFIG_FSL_LSCH3
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+ fdt_fixup_pcie(blob);
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+ #endif
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}
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#else
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