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@@ -0,0 +1,53 @@
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+// SPDX-License-Identifier: GPL-2.0+
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+/*
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+ * Copyright (C) 2020 SiFive, Inc
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+ *
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+ * Authors:
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+ * Pragnesh Patel <pragnesh.patel@sifive.com>
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+ */
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+
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+#include <common.h>
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+#include <asm/io.h>
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+#include <linux/bitops.h>
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+
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+/* Register offsets */
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+#define L2_CACHE_CONFIG 0x000
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+#define L2_CACHE_ENABLE 0x008
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+
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+#define MASK_NUM_WAYS GENMASK(15, 8)
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+#define NUM_WAYS_SHIFT 8
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+
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+DECLARE_GLOBAL_DATA_PTR;
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+
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+int cache_enable_ways(void)
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+{
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+ const void *blob = gd->fdt_blob;
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+ int node = (-FDT_ERR_NOTFOUND);
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+ fdt_addr_t base;
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+ u32 config;
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+ u32 ways;
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+
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+ volatile u32 *enable;
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+
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+ node = fdt_node_offset_by_compatible(blob, -1,
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+ "sifive,fu540-c000-ccache");
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+
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+ if (node < 0)
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+ return node;
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+
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+ base = fdtdec_get_addr(blob, node, "reg");
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+ if (base == FDT_ADDR_T_NONE)
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+ return FDT_ADDR_T_NONE;
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+
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+ config = readl((volatile u32 *)base + L2_CACHE_CONFIG);
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+ ways = (config & MASK_NUM_WAYS) >> NUM_WAYS_SHIFT;
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+
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+ enable = (volatile u32 *)(base + L2_CACHE_ENABLE);
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+
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+ /* memory barrier */
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+ mb();
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+ (*enable) = ways - 1;
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+ /* memory barrier */
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+ mb();
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+ return 0;
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+}
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