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@@ -1409,14 +1409,55 @@ pci_addr_t dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr,
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return bus_addr;
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}
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+static phys_addr_t dm_pci_map_ea_virt(struct udevice *dev, int ea_off,
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+ struct pci_child_platdata *pdata)
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+{
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+ phys_addr_t addr = 0;
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+
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+ /*
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+ * In the case of a Virtual Function device using BAR
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+ * base and size, add offset for VFn BAR(1, 2, 3...n)
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+ */
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+ if (pdata->is_virtfn) {
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+ size_t sz;
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+ u32 ea_entry;
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+
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+ /* MaxOffset, 1st DW */
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+ dm_pci_read_config32(dev, ea_off + 8, &ea_entry);
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+ sz = ea_entry & PCI_EA_FIELD_MASK;
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+ /* Fill up lower 2 bits */
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+ sz |= (~PCI_EA_FIELD_MASK);
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+
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+ if (ea_entry & PCI_EA_IS_64) {
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+ /* MaxOffset 2nd DW */
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+ dm_pci_read_config32(dev, ea_off + 16, &ea_entry);
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+ sz |= ((u64)ea_entry) << 32;
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+ }
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+
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+ addr = (pdata->virtid - 1) * (sz + 1);
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+ }
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+
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+ return addr;
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+}
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+
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static void *dm_pci_map_ea_bar(struct udevice *dev, int bar, int flags,
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- int ea_off)
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+ int ea_off, struct pci_child_platdata *pdata)
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{
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int ea_cnt, i, entry_size;
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int bar_id = (bar - PCI_BASE_ADDRESS_0) >> 2;
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u32 ea_entry;
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phys_addr_t addr;
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+ if (IS_ENABLED(CONFIG_PCI_SRIOV)) {
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+ /*
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+ * In the case of a Virtual Function device, device is
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+ * Physical function, so pdata will point to required VF
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+ * specific data.
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+ */
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+ if (pdata->is_virtfn)
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+ bar_id += PCI_EA_BEI_VF_BAR0;
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+ }
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+
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/* EA capability structure header */
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dm_pci_read_config32(dev, ea_off, &ea_entry);
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ea_cnt = (ea_entry >> 16) & PCI_EA_NUM_ENT_MASK;
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@@ -1439,6 +1480,9 @@ static void *dm_pci_map_ea_bar(struct udevice *dev, int bar, int flags,
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addr |= ((u64)ea_entry) << 32;
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}
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+ if (IS_ENABLED(CONFIG_PCI_SRIOV))
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+ addr += dm_pci_map_ea_virt(dev, ea_off, pdata);
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+
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/* size ignored for now */
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return map_physmem(addr, 0, flags);
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}
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@@ -1448,20 +1492,33 @@ static void *dm_pci_map_ea_bar(struct udevice *dev, int bar, int flags,
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void *dm_pci_map_bar(struct udevice *dev, int bar, int flags)
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{
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+ struct pci_child_platdata *pdata = dev_get_parent_platdata(dev);
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+ struct udevice *udev = dev;
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pci_addr_t pci_bus_addr;
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u32 bar_response;
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int ea_off;
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+ if (IS_ENABLED(CONFIG_PCI_SRIOV)) {
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+ /*
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+ * In case of Virtual Function devices, use PF udevice
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+ * as EA capability is defined in Physical Function
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+ */
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+ if (pdata->is_virtfn)
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+ udev = pdata->pfdev;
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+ }
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+
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/*
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* if the function supports Enhanced Allocation use that instead of
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* BARs
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+ * Incase of virtual functions, pdata will help read VF BEI
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+ * and EA entry size.
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*/
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- ea_off = dm_pci_find_capability(dev, PCI_CAP_ID_EA);
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+ ea_off = dm_pci_find_capability(udev, PCI_CAP_ID_EA);
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if (ea_off)
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- return dm_pci_map_ea_bar(dev, bar, flags, ea_off);
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+ return dm_pci_map_ea_bar(udev, bar, flags, ea_off, pdata);
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/* read BAR address */
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- dm_pci_read_config32(dev, bar, &bar_response);
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+ dm_pci_read_config32(udev, bar, &bar_response);
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pci_bus_addr = (pci_addr_t)(bar_response & ~0xf);
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/*
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@@ -1470,7 +1527,7 @@ void *dm_pci_map_bar(struct udevice *dev, int bar, int flags)
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* linear mapping. In the future, this could read the BAR size
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* and pass that as the size if needed.
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*/
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- return dm_pci_bus_to_virt(dev, pci_bus_addr, flags, 0, MAP_NOCACHE);
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+ return dm_pci_bus_to_virt(udev, pci_bus_addr, flags, 0, MAP_NOCACHE);
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}
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static int _dm_pci_find_next_capability(struct udevice *dev, u8 pos, int cap)
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