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@@ -0,0 +1,179 @@
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+// SPDX-License-Identifier: GPL-2.0
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+/*
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+ * Xilinx window watchdog timer driver.
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+ *
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+ * Author(s): Michal Simek <michal.simek@xilinx.com>
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+ * Ashok Reddy Soma <ashokred@xilinx.com>
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+ *
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+ * Copyright (c) 2020, Xilinx Inc.
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+ */
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+
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+#include <clk.h>
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+#include <common.h>
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+#include <dm.h>
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+#include <regmap.h>
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+#include <wdt.h>
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+#include <linux/compat.h>
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+#include <linux/io.h>
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+
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+/* Refresh Register Masks */
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+#define XWT_WWREF_GWRR_MASK BIT(0) /* Refresh and start new period */
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+
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+/* Generic Control/Status Register Masks */
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+#define XWT_WWCSR_GWEN_MASK BIT(0) /* Enable Bit */
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+
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+/* Register offsets for the Wdt device */
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+#define XWT_WWREF_OFFSET 0x1000 /* Refresh Register */
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+#define XWT_WWCSR_OFFSET 0x2000 /* Control/Status Register */
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+#define XWT_WWOFF_OFFSET 0x2008 /* Offset Register */
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+#define XWT_WWCMP0_OFFSET 0x2010 /* Compare Value Register0 */
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+#define XWT_WWCMP1_OFFSET 0x2014 /* Compare Value Register1 */
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+#define XWT_WWWRST_OFFSET 0x2FD0 /* Warm Reset Register */
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+
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+struct xlnx_wwdt_priv {
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+ bool enable_once;
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+ struct regmap *regs;
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+ struct clk clk;
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+};
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+
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+struct xlnx_wwdt_platdata {
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+ bool enable_once;
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+};
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+
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+static int xlnx_wwdt_reset(struct udevice *dev)
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+{
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+ struct xlnx_wwdt_priv *wdt = dev_get_priv(dev);
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+
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+ regmap_write(wdt->regs, XWT_WWREF_OFFSET, XWT_WWREF_GWRR_MASK);
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+
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+ return 0;
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+}
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+
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+static int xlnx_wwdt_stop(struct udevice *dev)
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+{
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+ u32 csr;
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+ struct xlnx_wwdt_priv *wdt = dev_get_priv(dev);
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+
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+ if (wdt->enable_once) {
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+ dev_warn(dev, "Can't stop Xilinx watchdog.\n");
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+ return -EBUSY;
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+ }
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+
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+ /* Disable the generic watchdog timer */
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+ regmap_read(wdt->regs, XWT_WWCSR_OFFSET, &csr);
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+ csr &= ~(XWT_WWCSR_GWEN_MASK);
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+ regmap_write(wdt->regs, XWT_WWCSR_OFFSET, csr);
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+
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+ clk_disable(&wdt->clk);
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+
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+ dev_dbg(dev, "Watchdog disabled!\n");
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+
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+ return 0;
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+}
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+
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+static int xlnx_wwdt_start(struct udevice *dev, u64 timeout, ulong flags)
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+{
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+ int ret;
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+ u32 csr;
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+ u64 count;
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+ unsigned long clock_f;
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+ struct xlnx_wwdt_priv *wdt = dev_get_priv(dev);
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+
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+ clock_f = clk_get_rate(&wdt->clk);
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+ if (IS_ERR_VALUE(clock_f)) {
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+ dev_err(dev, "failed to get rate\n");
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+ return clock_f;
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+ }
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+
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+ dev_dbg(dev, "%s: CLK %ld\n", __func__, clock_f);
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+
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+ /* Calculate timeout count */
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+ count = timeout * clock_f;
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+
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+ /* clk_enable will return -ENOSYS when it is not implemented */
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+ ret = clk_enable(&wdt->clk);
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+ if (ret && ret != -ENOSYS) {
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+ dev_err(dev, "failed to enable clock\n");
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+ return ret;
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+ }
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+
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+ /*
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+ * Timeout count is half as there are two windows
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+ * first window overflow is ignored (interrupt),
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+ * reset is only generated at second window overflow
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+ */
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+ count = count >> 1;
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+
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+ /* Disable the generic watchdog timer */
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+ regmap_read(wdt->regs, XWT_WWCSR_OFFSET, &csr);
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+ csr &= ~(XWT_WWCSR_GWEN_MASK);
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+ regmap_write(wdt->regs, XWT_WWCSR_OFFSET, csr);
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+
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+ /* Set compare and offset registers for generic watchdog timeout */
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+ regmap_write(wdt->regs, XWT_WWCMP0_OFFSET, (u32)count);
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+ regmap_write(wdt->regs, XWT_WWCMP1_OFFSET, 0);
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+ regmap_write(wdt->regs, XWT_WWOFF_OFFSET, (u32)count);
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+
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+ /* Enable the generic watchdog timer */
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+ regmap_read(wdt->regs, XWT_WWCSR_OFFSET, &csr);
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+ csr |= (XWT_WWCSR_GWEN_MASK);
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+ regmap_write(wdt->regs, XWT_WWCSR_OFFSET, csr);
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+
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+ return 0;
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+}
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+
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+static int xlnx_wwdt_probe(struct udevice *dev)
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+{
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+ int ret;
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+ struct xlnx_wwdt_platdata *platdata = dev_get_platdata(dev);
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+ struct xlnx_wwdt_priv *wdt = dev_get_priv(dev);
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+
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+ dev_dbg(dev, "%s: Probing wdt%u\n", __func__, dev->seq);
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+
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+ ret = regmap_init_mem(dev_ofnode(dev), &wdt->regs);
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+ if (ret) {
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+ dev_dbg(dev, "failed to get regbase of wwdt\n");
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+ return ret;
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+ }
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+
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+ wdt->enable_once = platdata->enable_once;
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+
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+ ret = clk_get_by_index(dev, 0, &wdt->clk);
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+ if (ret < 0)
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+ dev_err(dev, "failed to get clock\n");
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+
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+ return ret;
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+}
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+
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+static int xlnx_wwdt_ofdata_to_platdata(struct udevice *dev)
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+{
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+ struct xlnx_wwdt_platdata *platdata = dev_get_platdata(dev);
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+
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+ platdata->enable_once = dev_read_u32_default(dev,
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+ "xlnx,wdt-enable-once", 0);
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+ dev_dbg(dev, "wdt-enable-once %d\n", platdata->enable_once);
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+
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+ return 0;
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+}
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+
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+static const struct wdt_ops xlnx_wwdt_ops = {
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+ .start = xlnx_wwdt_start,
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+ .reset = xlnx_wwdt_reset,
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+ .stop = xlnx_wwdt_stop,
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+};
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+
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+static const struct udevice_id xlnx_wwdt_ids[] = {
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+ { .compatible = "xlnx,versal-wwdt-1.0", },
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+ {},
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+};
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+
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+U_BOOT_DRIVER(xlnx_wwdt) = {
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+ .name = "xlnx_wwdt",
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+ .id = UCLASS_WDT,
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+ .of_match = xlnx_wwdt_ids,
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+ .probe = xlnx_wwdt_probe,
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+ .priv_auto_alloc_size = sizeof(struct xlnx_wwdt_priv),
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+ .platdata_auto_alloc_size = sizeof(struct xlnx_wwdt_platdata),
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+ .ofdata_to_platdata = xlnx_wwdt_ofdata_to_platdata,
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+ .ops = &xlnx_wwdt_ops,
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+};
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