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+System Control and Management Interface (SCMI) Message Protocol
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+----------------------------------------------------------
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+
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+The SCMI is intended to allow agents such as OSPM to manage various functions
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+that are provided by the hardware platform it is running on, including power
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+and performance functions.
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+
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+This binding is intended to define the interface the firmware implementing
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+the SCMI as described in ARM document number ARM DEN 0056A ("ARM System Control
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+and Management Interface Platform Design Document")[0] provide for OSPM in
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+the device tree.
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+
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+Required properties:
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+
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+The scmi node with the following properties shall be under the /firmware/ node.
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+
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+- compatible : shall be "arm,scmi" or "arm,scmi-smc" for smc/hvc transports
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+- mboxes: List of phandle and mailbox channel specifiers. It should contain
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+ exactly one or two mailboxes, one for transmitting messages("tx")
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+ and another optional for receiving the notifications("rx") if
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+ supported.
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+- shmem : List of phandle pointing to the shared memory(SHM) area as per
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+ generic mailbox client binding.
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+- #address-cells : should be '1' if the device has sub-nodes, maps to
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+ protocol identifier for a given sub-node.
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+- #size-cells : should be '0' as 'reg' property doesn't have any size
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+ associated with it.
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+- arm,smc-id : SMC id required when using smc or hvc transports
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+
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+Optional properties:
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+
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+- mbox-names: shall be "tx" or "rx" depending on mboxes entries.
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+
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+See Documentation/devicetree/bindings/mailbox/mailbox.txt for more details
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+about the generic mailbox controller and client driver bindings.
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+
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+The mailbox is the only permitted method of calling the SCMI firmware.
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+Mailbox doorbell is used as a mechanism to alert the presence of a
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+messages and/or notification.
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+
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+Each protocol supported shall have a sub-node with corresponding compatible
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+as described in the following sections. If the platform supports dedicated
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+communication channel for a particular protocol, the 3 properties namely:
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+mboxes, mbox-names and shmem shall be present in the sub-node corresponding
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+to that protocol.
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+
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+Clock/Performance bindings for the clocks/OPPs based on SCMI Message Protocol
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+------------------------------------------------------------
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+
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+This binding uses the common clock binding[1].
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+
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+Required properties:
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+- #clock-cells : Should be 1. Contains the Clock ID value used by SCMI commands.
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+
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+Power domain bindings for the power domains based on SCMI Message Protocol
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+------------------------------------------------------------
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+
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+This binding for the SCMI power domain providers uses the generic power
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+domain binding[2].
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+
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+Required properties:
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+ - #power-domain-cells : Should be 1. Contains the device or the power
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+ domain ID value used by SCMI commands.
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+
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+Sensor bindings for the sensors based on SCMI Message Protocol
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+--------------------------------------------------------------
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+SCMI provides an API to access the various sensors on the SoC.
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+
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+Required properties:
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+- #thermal-sensor-cells: should be set to 1. This property follows the
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+ thermal device tree bindings[3].
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+
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+ Valid cell values are raw identifiers (Sensor ID)
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+ as used by the firmware. Refer to platform details
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+ for your implementation for the IDs to use.
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+
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+Reset signal bindings for the reset domains based on SCMI Message Protocol
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+------------------------------------------------------------
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+
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+This binding for the SCMI reset domain providers uses the generic reset
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+signal binding[5].
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+
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+Required properties:
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+ - #reset-cells : Should be 1. Contains the reset domain ID value used
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+ by SCMI commands.
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+
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+SRAM and Shared Memory for SCMI
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+-------------------------------
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+
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+A small area of SRAM is reserved for SCMI communication between application
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+processors and SCP.
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+
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+The properties should follow the generic mmio-sram description found in [4]
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+
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+Each sub-node represents the reserved area for SCMI.
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+
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+Required sub-node properties:
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+- reg : The base offset and size of the reserved area with the SRAM
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+- compatible : should be "arm,scmi-shmem" for Non-secure SRAM based
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+ shared memory
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+
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+[0] http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/index.html
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+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
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+[2] Documentation/devicetree/bindings/power/power-domain.yaml
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+[3] Documentation/devicetree/bindings/thermal/thermal.txt
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+[4] Documentation/devicetree/bindings/sram/sram.yaml
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+[5] Documentation/devicetree/bindings/reset/reset.txt
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+
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+Example:
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+
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+sram@50000000 {
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+ compatible = "mmio-sram";
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+ reg = <0x0 0x50000000 0x0 0x10000>;
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+
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ ranges = <0 0x0 0x50000000 0x10000>;
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+
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+ cpu_scp_lpri: scp-shmem@0 {
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+ compatible = "arm,scmi-shmem";
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+ reg = <0x0 0x200>;
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+ };
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+
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+ cpu_scp_hpri: scp-shmem@200 {
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+ compatible = "arm,scmi-shmem";
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+ reg = <0x200 0x200>;
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+ };
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+};
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+
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+mailbox@40000000 {
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+ ....
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+ #mbox-cells = <1>;
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+ reg = <0x0 0x40000000 0x0 0x10000>;
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+};
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+
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+firmware {
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+
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+ ...
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+
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+ scmi {
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+ compatible = "arm,scmi";
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+ mboxes = <&mailbox 0 &mailbox 1>;
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+ mbox-names = "tx", "rx";
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+ shmem = <&cpu_scp_lpri &cpu_scp_hpri>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ scmi_devpd: protocol@11 {
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+ reg = <0x11>;
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+ #power-domain-cells = <1>;
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+ };
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+
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+ scmi_dvfs: protocol@13 {
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+ reg = <0x13>;
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+ #clock-cells = <1>;
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+ };
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+
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+ scmi_clk: protocol@14 {
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+ reg = <0x14>;
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+ #clock-cells = <1>;
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+ };
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+
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+ scmi_sensors0: protocol@15 {
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+ reg = <0x15>;
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+ #thermal-sensor-cells = <1>;
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+ };
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+
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+ scmi_reset: protocol@16 {
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+ reg = <0x16>;
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+ #reset-cells = <1>;
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+ };
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+ };
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+};
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+
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+cpu@0 {
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+ ...
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+ reg = <0 0>;
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+ clocks = <&scmi_dvfs 0>;
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+};
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+
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+hdlcd@7ff60000 {
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+ ...
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+ reg = <0 0x7ff60000 0 0x1000>;
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+ clocks = <&scmi_clk 4>;
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+ power-domains = <&scmi_devpd 1>;
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+ resets = <&scmi_reset 10>;
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+};
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+
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+thermal-zones {
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+ soc_thermal {
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+ polling-delay-passive = <100>;
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+ polling-delay = <1000>;
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+ /* sensor ID */
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+ thermal-sensors = <&scmi_sensors0 3>;
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+ ...
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+ };
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+};
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