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@@ -150,24 +150,24 @@ static int omap3_wdt_reset(struct udevice *dev)
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{
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struct omap3_wdt_priv *priv = dev_get_priv(dev);
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-/*
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- * Somebody just triggered watchdog reset and write to WTGR register
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- * is in progress. It is resetting right now, no need to trigger it
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- * again
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- */
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+ /*
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+ * Somebody just triggered watchdog reset and write to WTGR register
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+ * is in progress. It is resetting right now, no need to trigger it
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+ * again
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+ */
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if ((readl(&priv->regs->wdtwwps)) & WDT_WWPS_PEND_WTGR)
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return 0;
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priv->wdt_trgr_pattern = ~(priv->wdt_trgr_pattern);
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writel(priv->wdt_trgr_pattern, &priv->regs->wdtwtgr);
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-/*
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- * Don't wait for posted write to complete, i.e. don't check
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- * WDT_WWPS_PEND_WTGR bit in WWPS register. There is no writes to
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- * WTGR register outside of this func, and if entering it
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- * we see WDT_WWPS_PEND_WTGR bit set, it means watchdog reset
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- * was just triggered. This prevents us from wasting time in busy
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- * polling of WDT_WWPS_PEND_WTGR bit.
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- */
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+ /*
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+ * Don't wait for posted write to complete, i.e. don't check
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+ * WDT_WWPS_PEND_WTGR bit in WWPS register. There is no writes to
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+ * WTGR register outside of this func, and if entering it
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+ * we see WDT_WWPS_PEND_WTGR bit set, it means watchdog reset
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+ * was just triggered. This prevents us from wasting time in busy
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+ * polling of WDT_WWPS_PEND_WTGR bit.
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+ */
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return 0;
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}
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@@ -175,7 +175,7 @@ static int omap3_wdt_stop(struct udevice *dev)
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{
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struct omap3_wdt_priv *priv = dev_get_priv(dev);
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-/* disable watchdog */
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+ /* disable watchdog */
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writel(0xAAAA, &priv->regs->wdtwspr);
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while (readl(&priv->regs->wdtwwps) != 0x0)
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;
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@@ -189,28 +189,28 @@ static int omap3_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags)
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{
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struct omap3_wdt_priv *priv = dev_get_priv(dev);
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u32 pre_margin = GET_WLDR_VAL(timeout_ms / 1000);
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-/*
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- * Make sure the watchdog is disabled. This is unfortunately required
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- * because writing to various registers with the watchdog running has no
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- * effect.
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- */
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+ /*
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+ * Make sure the watchdog is disabled. This is unfortunately required
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+ * because writing to various registers with the watchdog running has
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+ * no effect.
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+ */
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omap3_wdt_stop(dev);
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-/* initialize prescaler */
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+ /* initialize prescaler */
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while (readl(&priv->regs->wdtwwps) & WDT_WWPS_PEND_WCLR)
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;
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writel(WDT_WCLR_PRE | (PTV << WDT_WCLR_PTV_OFF), &priv->regs->wdtwclr);
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while (readl(&priv->regs->wdtwwps) & WDT_WWPS_PEND_WCLR)
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;
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-/* just count up at 32 KHz */
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+ /* just count up at 32 KHz */
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while (readl(&priv->regs->wdtwwps) & WDT_WWPS_PEND_WLDR)
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;
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writel(pre_margin, &priv->regs->wdtwldr);
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while (readl(&priv->regs->wdtwwps) & WDT_WWPS_PEND_WLDR)
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;
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-/* Sequence to enable the watchdog */
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+ /* Sequence to enable the watchdog */
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writel(0xBBBB, &priv->regs->wdtwspr);
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while ((readl(&priv->regs->wdtwwps)) & WDT_WWPS_PEND_WSPR)
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;
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