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@@ -7,6 +7,100 @@
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*/
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#include <common.h>
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+#include <dm/device.h>
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+#include <fdt_support.h>
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+
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+#ifdef CONFIG_ARM64
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+#include <asm/armv8/mmu.h>
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+
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+static struct mm_region bcm283x_mem_map[] = {
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+ {
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+ .virt = 0x00000000UL,
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+ .phys = 0x00000000UL,
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+ .size = 0x3f000000UL,
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+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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+ PTE_BLOCK_INNER_SHARE
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+ }, {
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+ .virt = 0x3f000000UL,
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+ .phys = 0x3f000000UL,
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+ .size = 0x01000000UL,
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+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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+ PTE_BLOCK_NON_SHARE |
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+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
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+ }, {
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+ /* List terminator */
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+ 0,
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+ }
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+};
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+
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+static struct mm_region bcm2711_mem_map[] = {
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+ {
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+ .virt = 0x00000000UL,
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+ .phys = 0x00000000UL,
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+ .size = 0xfe000000UL,
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+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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+ PTE_BLOCK_INNER_SHARE
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+ }, {
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+ .virt = 0xfe000000UL,
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+ .phys = 0xfe000000UL,
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+ .size = 0x01800000UL,
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+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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+ PTE_BLOCK_NON_SHARE |
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+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
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+ }, {
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+ /* List terminator */
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+ 0,
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+ }
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+};
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+
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+struct mm_region *mem_map = bcm283x_mem_map;
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+
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+/*
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+ * I/O address space varies on different chip versions.
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+ * We set the base address by inspecting the DTB.
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+ */
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+static const struct udevice_id board_ids[] = {
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+ { .compatible = "brcm,bcm2837", .data = (ulong)&bcm283x_mem_map},
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+ { .compatible = "brcm,bcm2838", .data = (ulong)&bcm2711_mem_map},
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+ { .compatible = "brcm,bcm2711", .data = (ulong)&bcm2711_mem_map},
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+ { },
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+};
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+
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+static void _rpi_update_mem_map(struct mm_region *pd)
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+{
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+ int i;
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+
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+ for (i = 0; i < 2; i++) {
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+ mem_map[i].virt = pd[i].virt;
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+ mem_map[i].phys = pd[i].phys;
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+ mem_map[i].size = pd[i].size;
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+ mem_map[i].attrs = pd[i].attrs;
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+ }
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+}
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+
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+static void rpi_update_mem_map(void)
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+{
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+ int ret;
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+ struct mm_region *mm;
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+ const struct udevice_id *of_match = board_ids;
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+
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+ while (of_match->compatible) {
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+ ret = fdt_node_check_compatible(gd->fdt_blob, 0,
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+ of_match->compatible);
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+ if (!ret) {
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+ mm = (struct mm_region *)of_match->data;
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+ _rpi_update_mem_map(mm);
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+ break;
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+ }
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+
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+ of_match++;
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+ }
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+}
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+#else
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+static void rpi_update_mem_map(void) {}
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+#endif
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+
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+unsigned long rpi_bcm283x_base = 0x3f000000;
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int arch_cpu_init(void)
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{
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@@ -15,6 +109,28 @@ int arch_cpu_init(void)
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return 0;
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}
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+int mach_cpu_init(void)
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+{
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+ int ret, soc_offset;
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+ u64 io_base, size;
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+
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+ rpi_update_mem_map();
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+
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+ /* Get IO base from device tree */
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+ soc_offset = fdt_path_offset(gd->fdt_blob, "/soc");
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+ if (soc_offset < 0)
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+ return soc_offset;
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+
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+ ret = fdt_read_range((void *)gd->fdt_blob, soc_offset, 0, NULL,
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+ &io_base, &size);
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+ if (ret)
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+ return ret;
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+
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+ rpi_bcm283x_base = io_base;
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+
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+ return 0;
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+}
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+
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#ifdef CONFIG_ARMV7_LPAE
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void enable_caches(void)
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{
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